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Thu, 08 Jul 2021 08:08:51 -0700 (PDT) Received: from [192.168.1.11] ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id g12sm10675762pjk.25.2021.07.08.08.08.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 08 Jul 2021 08:08:50 -0700 (PDT) Subject: Re: [PATCH] target/arm: Implement MTE3 To: Peter Collingbourne References: <20210611190653.754648-1-pcc@google.com> From: Richard Henderson Message-ID: <1b726e8c-5f6d-856e-72c1-8d835f28aec2@linaro.org> Date: Thu, 8 Jul 2021 08:08:47 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210611190653.754648-1-pcc@google.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Vincenzo Frascino , qemu-devel@nongnu.org, Evgenii Stepanov Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Cc: Peter. r~ On 6/11/21 12:06 PM, Peter Collingbourne wrote: > MTE3 introduces an asymmetric tag checking mode, in which loads are > checked synchronously and stores are checked asynchronously. Add > support for it. > > Signed-off-by: Peter Collingbourne > --- > target/arm/cpu64.c | 2 +- > target/arm/mte_helper.c | 83 ++++++++++++++++++++++++++--------------- > 2 files changed, 53 insertions(+), 32 deletions(-) > > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index 1c23187d1a..c7a1626bec 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -683,7 +683,7 @@ static void aarch64_max_initfn(Object *obj) > * during realize if the board provides no tag memory, much like > * we do for EL2 with the virtualization=on property. > */ > - t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); > + t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); > cpu->isar.id_aa64pfr1 = t; > > t = cpu->isar.id_aa64mmfr0; > diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c > index 166b9d260f..7b76d871ff 100644 > --- a/target/arm/mte_helper.c > +++ b/target/arm/mte_helper.c > @@ -538,13 +538,51 @@ void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val) > } > } > > +static void mte_sync_check_fail(CPUARMState *env, uint32_t desc, > + uint64_t dirty_ptr, uintptr_t ra) > +{ > + int is_write, syn; > + > + env->exception.vaddress = dirty_ptr; > + > + is_write = FIELD_EX32(desc, MTEDESC, WRITE); > + syn = syn_data_abort_no_iss(arm_current_el(env) != 0, 0, 0, 0, 0, is_write, > + 0x11); > + raise_exception_ra(env, EXCP_DATA_ABORT, syn, exception_target_el(env), ra); > + g_assert_not_reached(); > +} > + > +static void mte_async_check_fail(CPUARMState *env, uint32_t desc, > + uint64_t dirty_ptr, uintptr_t ra, > + ARMMMUIdx arm_mmu_idx, int el) > +{ > + int select; > + > + if (regime_has_2_ranges(arm_mmu_idx)) { > + select = extract64(dirty_ptr, 55, 1); > + } else { > + select = 0; > + } > + env->cp15.tfsr_el[el] |= 1 << select; > +#ifdef CONFIG_USER_ONLY > + /* > + * Stand in for a timer irq, setting _TIF_MTE_ASYNC_FAULT, > + * which then sends a SIGSEGV when the thread is next scheduled. > + * This cpu will return to the main loop at the end of the TB, > + * which is rather sooner than "normal". But the alternative > + * is waiting until the next syscall. > + */ > + qemu_cpu_kick(env_cpu(env)); > +#endif > +} > + > /* Record a tag check failure. */ > static void mte_check_fail(CPUARMState *env, uint32_t desc, > uint64_t dirty_ptr, uintptr_t ra) > { > int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); > ARMMMUIdx arm_mmu_idx = core_to_aa64_mmu_idx(mmu_idx); > - int el, reg_el, tcf, select, is_write, syn; > + int el, reg_el, tcf; > uint64_t sctlr; > > reg_el = regime_el(env, arm_mmu_idx); > @@ -564,14 +602,8 @@ static void mte_check_fail(CPUARMState *env, uint32_t desc, > switch (tcf) { > case 1: > /* Tag check fail causes a synchronous exception. */ > - env->exception.vaddress = dirty_ptr; > - > - is_write = FIELD_EX32(desc, MTEDESC, WRITE); > - syn = syn_data_abort_no_iss(arm_current_el(env) != 0, 0, 0, 0, 0, > - is_write, 0x11); > - raise_exception_ra(env, EXCP_DATA_ABORT, syn, > - exception_target_el(env), ra); > - /* noreturn, but fall through to the assert anyway */ > + mte_sync_check_fail(env, desc, dirty_ptr, ra); > + break; > > case 0: > /* > @@ -583,30 +615,19 @@ static void mte_check_fail(CPUARMState *env, uint32_t desc, > > case 2: > /* Tag check fail causes asynchronous flag set. */ > - if (regime_has_2_ranges(arm_mmu_idx)) { > - select = extract64(dirty_ptr, 55, 1); > - } else { > - select = 0; > - } > - env->cp15.tfsr_el[el] |= 1 << select; > -#ifdef CONFIG_USER_ONLY > - /* > - * Stand in for a timer irq, setting _TIF_MTE_ASYNC_FAULT, > - * which then sends a SIGSEGV when the thread is next scheduled. > - * This cpu will return to the main loop at the end of the TB, > - * which is rather sooner than "normal". But the alternative > - * is waiting until the next syscall. > - */ > - qemu_cpu_kick(env_cpu(env)); > -#endif > + mte_async_check_fail(env, desc, dirty_ptr, ra, arm_mmu_idx, el); > break; > > - default: > - /* Case 3: Reserved. */ > - qemu_log_mask(LOG_GUEST_ERROR, > - "Tag check failure with SCTLR_EL%d.TCF%s " > - "set to reserved value %d\n", > - reg_el, el ? "" : "0", tcf); > + case 3: > + /* > + * Tag check fail causes asynchronous flag set for stores, or > + * a synchronous exception for loads. > + */ > + if (FIELD_EX32(desc, MTEDESC, WRITE)) { > + mte_async_check_fail(env, desc, dirty_ptr, ra, arm_mmu_idx, el); > + } else { > + mte_sync_check_fail(env, desc, dirty_ptr, ra); > + } > break; > } > } >