Hi all,

On  27 Aug, this message from Adrian Cox echoed through cyberspace:
> Michel Lanners wrote:
>> It seems that the effect of the L2CR[DO] bit isn't clear.
> 
> I think I posted a patch for this a while ago, but I've sort of lost
> track. Basically, somebody in Motorola's documentation department
> couldn't tell one from zero. In normal use the bit should be clear.
> Hopefully somebody with write access will get the correct form into CVS.

Ok, so I understood it the right way.

Paul, below is a patch that fixes this, adds a few more bit
interpretations, and tries to clean up a bit the code and the display.
I've checked, even if everything is printed, we're staying within the
temp buffer ;-).

On  27 Aug, this message from Marc Dietrich echoed through cyberspace:
> I downloaded the 750 PDF Manuel and to Bit #9 (L2DO) it says:
> "L2 Data-only. Setting this bit enables data-only operation in the L2
> cache..."                                    ^^^^

Ok, found it. The above is in chapter 2; the less-verbose table in
chapter 9 has it wrong.

> So setting this bit disables instruction caching therefore it should'nt be
> set on bootup. 

Yep.

> It seems to me, that the L2CR programming is implemented but disabled in
> current kernel version. The L2CR=xxxxxxx doesn't work for me.

The coammnd-line option doesn't work; there is a function for parsing
this option, but it is never called. However, there is
/proc/sys/kernel/l2cr, which is readable _and_ writable. So
echo 0 > /proc/sys/kernel/l2cr disables the L2.

> By the way, it seems that Motola (or IBM) uses different cache chips on
> the 750 CPU - one with 0.5 and one with 1.0 ns timings. 0.5 ns are the
> common used chips while mine has a 1.0ns timing. This causes the
> PowerLogix Cache Control to crash my Mac. Has anyone expiriances on this?
> How has this been to recocnice in the kernel boot-up?

There is no way I know of for autodetecting any attribute of the L2
cache (except the size, maybe). All values have to be set based on some
non-automatic identification, i.e mostly manually.

On  27 Aug, this message from Benjamin Herrenschmidt echoed through cyberspace:
> Don't forget the inverted numbering of bits usually used by Moto.

Yeah; that annoyed me as well; but it is pretty obvious if you cat
/proc/sys/kernel/l2cr.

> Also, you may want to set the invalidate bit when setting l2cr. Note also
> that the _set_l2cr routine in the kernel alrady handles some of the bits.

I learned that the lock-up way ;-) Shouldn't _set_l2cr() check whether
we're switching the cache on, and if so, do the invalidate for us?

> BTW. Paul, did you merge the latest code from PowerLogix I sent you a
> couple of weeks ago ?

2.2.12 contains a patch to this code.

Michel

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