From: Michel Lanners <mlan@cpu.lu>
To: linuxppc-dev@lists.linuxppc.org
Subject: bug in l2cr status display?
Date: Thu, 26 Aug 1999 23:05:40 +0200 (CEST) [thread overview]
Message-ID: <199908262105.XAA03192@piglet.cpu.lu> (raw)
Hi all,
While playing with the l2cr in order to set it manually after OF
booting, I've come across the following.
It seems that the effect of the L2CR[DO] bit isn't clear. In the 750
user manual, in the table describing l2cr, it says '... setting this
bit enables the caching of instructions'. This doesn't corrsspond to
the name of the register, nor to what I see with my G3 upgrade card: in
normal operation, L2CR[DO] isn't set, but it makes no sense to disable
instruction caching excpet for test purposes.
So, what's happening? Is the user manual wrong? In that case, we should
correct arch/ppc/kernel/ppc_htab.c accordingly.
Any Motorola engineer around? Others with better docs? FWIW, I checked
the 750 errata already... nothing.
Michel
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next reply other threads:[~1999-08-26 21:05 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
1999-08-26 21:05 Michel Lanners [this message]
1999-08-27 8:24 ` bug in l2cr status display? Adrian Cox
1999-08-27 18:07 ` Michel Lanners
-- strict thread matches above, loose matches on Subject: below --
1999-08-27 13:09 Marc Dietrich
1999-08-27 20:28 ` Benjamin Herrenschmidt
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