* [PATCH] irqchip/riscv-intc: Fix use of AIA IRQs 32-63 on riscv32
@ 2024-03-12 21:28 ` Samuel Holland
0 siblings, 0 replies; 8+ messages in thread
From: Samuel Holland @ 2024-03-12 21:28 UTC (permalink / raw
To: Anup Patel, Thomas Gleixner
Cc: Samuel Holland, Albert Ou, Palmer Dabbelt, Paul Walmsley,
linux-kernel, linux-riscv
riscv_intc_custom_base is initialized to BITS_PER_LONG, so the second
check passes even though AIA provides 64 IRQs. Adjust the condition to
only check the custom IRQ range for IRQs outside the standard range, and
adjust the standard range when AIA is available.
Fixes: bb7921cdea12 ("irqchip/riscv-intc: Add support for RISC-V AIA")
Fixes: e6bd9b966dc8 ("irqchip/riscv-intc: Fix low-level interrupt handler setup for AIA")
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
drivers/irqchip/irq-riscv-intc.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index f87aeab460eb..9e71c4428814 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -149,8 +149,9 @@ static int riscv_intc_domain_alloc(struct irq_domain *domain,
* Only allow hwirq for which we have corresponding standard or
* custom interrupt enable register.
*/
- if ((hwirq >= riscv_intc_nr_irqs && hwirq < riscv_intc_custom_base) ||
- (hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs))
+ if (hwirq >= riscv_intc_nr_irqs &&
+ (hwirq < riscv_intc_custom_base ||
+ hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs))
return -EINVAL;
for (i = 0; i < nr_irqs; i++) {
@@ -183,10 +184,12 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn, struct irq_ch
return -ENXIO;
}
- if (riscv_isa_extension_available(NULL, SxAIA))
+ if (riscv_isa_extension_available(NULL, SxAIA)) {
+ riscv_intc_nr_irqs = 64;
rc = set_handle_irq(&riscv_intc_aia_irq);
- else
+ } else {
rc = set_handle_irq(&riscv_intc_irq);
+ }
if (rc) {
pr_err("failed to set irq handler\n");
return rc;
@@ -195,7 +198,7 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn, struct irq_ch
riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
pr_info("%d local interrupts mapped%s\n",
- riscv_isa_extension_available(NULL, SxAIA) ? 64 : riscv_intc_nr_irqs,
+ riscv_intc_nr_irqs,
riscv_isa_extension_available(NULL, SxAIA) ? " using AIA" : "");
if (riscv_intc_custom_nr_irqs)
pr_info("%d custom local interrupts mapped\n", riscv_intc_custom_nr_irqs);
--
2.43.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] irqchip/riscv-intc: Fix use of AIA IRQs 32-63 on riscv32
@ 2024-03-12 21:28 ` Samuel Holland
0 siblings, 0 replies; 8+ messages in thread
From: Samuel Holland @ 2024-03-12 21:28 UTC (permalink / raw
To: Anup Patel, Thomas Gleixner
Cc: Samuel Holland, Albert Ou, Palmer Dabbelt, Paul Walmsley,
linux-kernel, linux-riscv
riscv_intc_custom_base is initialized to BITS_PER_LONG, so the second
check passes even though AIA provides 64 IRQs. Adjust the condition to
only check the custom IRQ range for IRQs outside the standard range, and
adjust the standard range when AIA is available.
Fixes: bb7921cdea12 ("irqchip/riscv-intc: Add support for RISC-V AIA")
Fixes: e6bd9b966dc8 ("irqchip/riscv-intc: Fix low-level interrupt handler setup for AIA")
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
drivers/irqchip/irq-riscv-intc.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index f87aeab460eb..9e71c4428814 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -149,8 +149,9 @@ static int riscv_intc_domain_alloc(struct irq_domain *domain,
* Only allow hwirq for which we have corresponding standard or
* custom interrupt enable register.
*/
- if ((hwirq >= riscv_intc_nr_irqs && hwirq < riscv_intc_custom_base) ||
- (hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs))
+ if (hwirq >= riscv_intc_nr_irqs &&
+ (hwirq < riscv_intc_custom_base ||
+ hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs))
return -EINVAL;
for (i = 0; i < nr_irqs; i++) {
@@ -183,10 +184,12 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn, struct irq_ch
return -ENXIO;
}
- if (riscv_isa_extension_available(NULL, SxAIA))
+ if (riscv_isa_extension_available(NULL, SxAIA)) {
+ riscv_intc_nr_irqs = 64;
rc = set_handle_irq(&riscv_intc_aia_irq);
- else
+ } else {
rc = set_handle_irq(&riscv_intc_irq);
+ }
if (rc) {
pr_err("failed to set irq handler\n");
return rc;
@@ -195,7 +198,7 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn, struct irq_ch
riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
pr_info("%d local interrupts mapped%s\n",
- riscv_isa_extension_available(NULL, SxAIA) ? 64 : riscv_intc_nr_irqs,
+ riscv_intc_nr_irqs,
riscv_isa_extension_available(NULL, SxAIA) ? " using AIA" : "");
if (riscv_intc_custom_nr_irqs)
pr_info("%d custom local interrupts mapped\n", riscv_intc_custom_nr_irqs);
--
2.43.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] irqchip/riscv-intc: Fix use of AIA IRQs 32-63 on riscv32
2024-03-12 21:28 ` Samuel Holland
@ 2024-03-13 4:34 ` Anup Patel
-1 siblings, 0 replies; 8+ messages in thread
From: Anup Patel @ 2024-03-13 4:34 UTC (permalink / raw
To: Samuel Holland
Cc: Thomas Gleixner, Albert Ou, Palmer Dabbelt, Paul Walmsley,
linux-kernel, linux-riscv
On Wed, Mar 13, 2024 at 2:58 AM Samuel Holland
<samuel.holland@sifive.com> wrote:
>
> riscv_intc_custom_base is initialized to BITS_PER_LONG, so the second
> check passes even though AIA provides 64 IRQs. Adjust the condition to
> only check the custom IRQ range for IRQs outside the standard range, and
> adjust the standard range when AIA is available.
>
> Fixes: bb7921cdea12 ("irqchip/riscv-intc: Add support for RISC-V AIA")
> Fixes: e6bd9b966dc8 ("irqchip/riscv-intc: Fix low-level interrupt handler setup for AIA")
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
I missed adjusting riscv_intc_nr_irqs in commit e6bd9b966dc8.
Thanks for catching.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
>
> drivers/irqchip/irq-riscv-intc.c | 13 ++++++++-----
> 1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> index f87aeab460eb..9e71c4428814 100644
> --- a/drivers/irqchip/irq-riscv-intc.c
> +++ b/drivers/irqchip/irq-riscv-intc.c
> @@ -149,8 +149,9 @@ static int riscv_intc_domain_alloc(struct irq_domain *domain,
> * Only allow hwirq for which we have corresponding standard or
> * custom interrupt enable register.
> */
> - if ((hwirq >= riscv_intc_nr_irqs && hwirq < riscv_intc_custom_base) ||
> - (hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs))
> + if (hwirq >= riscv_intc_nr_irqs &&
> + (hwirq < riscv_intc_custom_base ||
> + hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs))
> return -EINVAL;
>
> for (i = 0; i < nr_irqs; i++) {
> @@ -183,10 +184,12 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn, struct irq_ch
> return -ENXIO;
> }
>
> - if (riscv_isa_extension_available(NULL, SxAIA))
> + if (riscv_isa_extension_available(NULL, SxAIA)) {
> + riscv_intc_nr_irqs = 64;
> rc = set_handle_irq(&riscv_intc_aia_irq);
> - else
> + } else {
> rc = set_handle_irq(&riscv_intc_irq);
> + }
> if (rc) {
> pr_err("failed to set irq handler\n");
> return rc;
> @@ -195,7 +198,7 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn, struct irq_ch
> riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
>
> pr_info("%d local interrupts mapped%s\n",
> - riscv_isa_extension_available(NULL, SxAIA) ? 64 : riscv_intc_nr_irqs,
> + riscv_intc_nr_irqs,
> riscv_isa_extension_available(NULL, SxAIA) ? " using AIA" : "");
> if (riscv_intc_custom_nr_irqs)
> pr_info("%d custom local interrupts mapped\n", riscv_intc_custom_nr_irqs);
> --
> 2.43.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] irqchip/riscv-intc: Fix use of AIA IRQs 32-63 on riscv32
@ 2024-03-13 4:34 ` Anup Patel
0 siblings, 0 replies; 8+ messages in thread
From: Anup Patel @ 2024-03-13 4:34 UTC (permalink / raw
To: Samuel Holland
Cc: Thomas Gleixner, Albert Ou, Palmer Dabbelt, Paul Walmsley,
linux-kernel, linux-riscv
On Wed, Mar 13, 2024 at 2:58 AM Samuel Holland
<samuel.holland@sifive.com> wrote:
>
> riscv_intc_custom_base is initialized to BITS_PER_LONG, so the second
> check passes even though AIA provides 64 IRQs. Adjust the condition to
> only check the custom IRQ range for IRQs outside the standard range, and
> adjust the standard range when AIA is available.
>
> Fixes: bb7921cdea12 ("irqchip/riscv-intc: Add support for RISC-V AIA")
> Fixes: e6bd9b966dc8 ("irqchip/riscv-intc: Fix low-level interrupt handler setup for AIA")
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
I missed adjusting riscv_intc_nr_irqs in commit e6bd9b966dc8.
Thanks for catching.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
>
> drivers/irqchip/irq-riscv-intc.c | 13 ++++++++-----
> 1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> index f87aeab460eb..9e71c4428814 100644
> --- a/drivers/irqchip/irq-riscv-intc.c
> +++ b/drivers/irqchip/irq-riscv-intc.c
> @@ -149,8 +149,9 @@ static int riscv_intc_domain_alloc(struct irq_domain *domain,
> * Only allow hwirq for which we have corresponding standard or
> * custom interrupt enable register.
> */
> - if ((hwirq >= riscv_intc_nr_irqs && hwirq < riscv_intc_custom_base) ||
> - (hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs))
> + if (hwirq >= riscv_intc_nr_irqs &&
> + (hwirq < riscv_intc_custom_base ||
> + hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs))
> return -EINVAL;
>
> for (i = 0; i < nr_irqs; i++) {
> @@ -183,10 +184,12 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn, struct irq_ch
> return -ENXIO;
> }
>
> - if (riscv_isa_extension_available(NULL, SxAIA))
> + if (riscv_isa_extension_available(NULL, SxAIA)) {
> + riscv_intc_nr_irqs = 64;
> rc = set_handle_irq(&riscv_intc_aia_irq);
> - else
> + } else {
> rc = set_handle_irq(&riscv_intc_irq);
> + }
> if (rc) {
> pr_err("failed to set irq handler\n");
> return rc;
> @@ -195,7 +198,7 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn, struct irq_ch
> riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
>
> pr_info("%d local interrupts mapped%s\n",
> - riscv_isa_extension_available(NULL, SxAIA) ? 64 : riscv_intc_nr_irqs,
> + riscv_intc_nr_irqs,
> riscv_isa_extension_available(NULL, SxAIA) ? " using AIA" : "");
> if (riscv_intc_custom_nr_irqs)
> pr_info("%d custom local interrupts mapped\n", riscv_intc_custom_nr_irqs);
> --
> 2.43.1
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
* [tip: irq/urgent] irqchip/riscv-intc: Fix use of AIA interrupts 32-63 on riscv32
2024-03-12 21:28 ` Samuel Holland
(?)
(?)
@ 2024-03-13 10:55 ` tip-bot2 for Samuel Holland
-1 siblings, 0 replies; 8+ messages in thread
From: tip-bot2 for Samuel Holland @ 2024-03-13 10:55 UTC (permalink / raw
To: linux-tip-commits
Cc: Samuel Holland, Thomas Gleixner, Anup Patel, x86, linux-kernel,
maz
The following commit has been merged into the irq/urgent branch of tip:
Commit-ID: 4ce937160ba053789f96d5130d5de4deaee2ad23
Gitweb: https://git.kernel.org/tip/4ce937160ba053789f96d5130d5de4deaee2ad23
Author: Samuel Holland <samuel.holland@sifive.com>
AuthorDate: Tue, 12 Mar 2024 14:28:08 -07:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Wed, 13 Mar 2024 11:50:11 +01:00
irqchip/riscv-intc: Fix use of AIA interrupts 32-63 on riscv32
riscv_intc_custom_base is initialized to BITS_PER_LONG, so the second
check passes even though AIA provides 64 interrupts. Adjust the condition to
only check the custom range for interrupts outside the standard range, and
adjust the standard range when AIA is available.
Fixes: bb7921cdea12 ("irqchip/riscv-intc: Add support for RISC-V AIA")
Fixes: e6bd9b966dc8 ("irqchip/riscv-intc: Fix low-level interrupt handler setup for AIA")
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20240312212813.2323841-1-samuel.holland@sifive.com
---
drivers/irqchip/irq-riscv-intc.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index f87aeab..9e71c44 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -149,8 +149,9 @@ static int riscv_intc_domain_alloc(struct irq_domain *domain,
* Only allow hwirq for which we have corresponding standard or
* custom interrupt enable register.
*/
- if ((hwirq >= riscv_intc_nr_irqs && hwirq < riscv_intc_custom_base) ||
- (hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs))
+ if (hwirq >= riscv_intc_nr_irqs &&
+ (hwirq < riscv_intc_custom_base ||
+ hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs))
return -EINVAL;
for (i = 0; i < nr_irqs; i++) {
@@ -183,10 +184,12 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn, struct irq_ch
return -ENXIO;
}
- if (riscv_isa_extension_available(NULL, SxAIA))
+ if (riscv_isa_extension_available(NULL, SxAIA)) {
+ riscv_intc_nr_irqs = 64;
rc = set_handle_irq(&riscv_intc_aia_irq);
- else
+ } else {
rc = set_handle_irq(&riscv_intc_irq);
+ }
if (rc) {
pr_err("failed to set irq handler\n");
return rc;
@@ -195,7 +198,7 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn, struct irq_ch
riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
pr_info("%d local interrupts mapped%s\n",
- riscv_isa_extension_available(NULL, SxAIA) ? 64 : riscv_intc_nr_irqs,
+ riscv_intc_nr_irqs,
riscv_isa_extension_available(NULL, SxAIA) ? " using AIA" : "");
if (riscv_intc_custom_nr_irqs)
pr_info("%d custom local interrupts mapped\n", riscv_intc_custom_nr_irqs);
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [tip: irq/urgent] irqchip/riscv-intc: Fix use of AIA interrupts 32-63 on riscv32
2024-03-12 21:28 ` Samuel Holland
` (2 preceding siblings ...)
(?)
@ 2024-03-15 18:54 ` tip-bot2 for Samuel Holland
-1 siblings, 0 replies; 8+ messages in thread
From: tip-bot2 for Samuel Holland @ 2024-03-15 18:54 UTC (permalink / raw
To: linux-tip-commits
Cc: Samuel Holland, Thomas Gleixner, Anup Patel, x86, linux-kernel,
maz
The following commit has been merged into the irq/urgent branch of tip:
Commit-ID: ca5b0b717b75d0f86f7f5dfe18369781bec742ad
Gitweb: https://git.kernel.org/tip/ca5b0b717b75d0f86f7f5dfe18369781bec742ad
Author: Samuel Holland <samuel.holland@sifive.com>
AuthorDate: Tue, 12 Mar 2024 14:28:08 -07:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Fri, 15 Mar 2024 15:27:02 +01:00
irqchip/riscv-intc: Fix use of AIA interrupts 32-63 on riscv32
riscv_intc_custom_base is initialized to BITS_PER_LONG, so the second
check passes even though AIA provides 64 interrupts. Adjust the condition to
only check the custom range for interrupts outside the standard range, and
adjust the standard range when AIA is available.
Fixes: 3c46fc5b5507 ("irqchip/riscv-intc: Add support for RISC-V AIA")
Fixes: 678c607ecf8a ("irqchip/riscv-intc: Fix low-level interrupt handler setup for AIA")
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20240312212813.2323841-1-samuel.holland@sifive.com
---
drivers/irqchip/irq-riscv-intc.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index f87aeab..9e71c44 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -149,8 +149,9 @@ static int riscv_intc_domain_alloc(struct irq_domain *domain,
* Only allow hwirq for which we have corresponding standard or
* custom interrupt enable register.
*/
- if ((hwirq >= riscv_intc_nr_irqs && hwirq < riscv_intc_custom_base) ||
- (hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs))
+ if (hwirq >= riscv_intc_nr_irqs &&
+ (hwirq < riscv_intc_custom_base ||
+ hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs))
return -EINVAL;
for (i = 0; i < nr_irqs; i++) {
@@ -183,10 +184,12 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn, struct irq_ch
return -ENXIO;
}
- if (riscv_isa_extension_available(NULL, SxAIA))
+ if (riscv_isa_extension_available(NULL, SxAIA)) {
+ riscv_intc_nr_irqs = 64;
rc = set_handle_irq(&riscv_intc_aia_irq);
- else
+ } else {
rc = set_handle_irq(&riscv_intc_irq);
+ }
if (rc) {
pr_err("failed to set irq handler\n");
return rc;
@@ -195,7 +198,7 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn, struct irq_ch
riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
pr_info("%d local interrupts mapped%s\n",
- riscv_isa_extension_available(NULL, SxAIA) ? 64 : riscv_intc_nr_irqs,
+ riscv_intc_nr_irqs,
riscv_isa_extension_available(NULL, SxAIA) ? " using AIA" : "");
if (riscv_intc_custom_nr_irqs)
pr_info("%d custom local interrupts mapped\n", riscv_intc_custom_nr_irqs);
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] irqchip/riscv-intc: Fix use of AIA IRQs 32-63 on riscv32
2024-03-12 21:28 ` Samuel Holland
@ 2024-03-25 4:42 ` patchwork-bot+linux-riscv
-1 siblings, 0 replies; 8+ messages in thread
From: patchwork-bot+linux-riscv @ 2024-03-25 4:42 UTC (permalink / raw
To: Samuel Holland
Cc: linux-riscv, anup, tglx, aou, palmer, paul.walmsley, linux-kernel
Hello:
This patch was applied to riscv/linux.git (fixes)
by Thomas Gleixner <tglx@linutronix.de>:
On Tue, 12 Mar 2024 14:28:08 -0700 you wrote:
> riscv_intc_custom_base is initialized to BITS_PER_LONG, so the second
> check passes even though AIA provides 64 IRQs. Adjust the condition to
> only check the custom IRQ range for IRQs outside the standard range, and
> adjust the standard range when AIA is available.
>
> Fixes: bb7921cdea12 ("irqchip/riscv-intc: Add support for RISC-V AIA")
> Fixes: e6bd9b966dc8 ("irqchip/riscv-intc: Fix low-level interrupt handler setup for AIA")
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
>
> [...]
Here is the summary with links:
- irqchip/riscv-intc: Fix use of AIA IRQs 32-63 on riscv32
https://git.kernel.org/riscv/c/ca5b0b717b75
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] irqchip/riscv-intc: Fix use of AIA IRQs 32-63 on riscv32
@ 2024-03-25 4:42 ` patchwork-bot+linux-riscv
0 siblings, 0 replies; 8+ messages in thread
From: patchwork-bot+linux-riscv @ 2024-03-25 4:42 UTC (permalink / raw
To: Samuel Holland
Cc: linux-riscv, anup, tglx, aou, palmer, paul.walmsley, linux-kernel
Hello:
This patch was applied to riscv/linux.git (fixes)
by Thomas Gleixner <tglx@linutronix.de>:
On Tue, 12 Mar 2024 14:28:08 -0700 you wrote:
> riscv_intc_custom_base is initialized to BITS_PER_LONG, so the second
> check passes even though AIA provides 64 IRQs. Adjust the condition to
> only check the custom IRQ range for IRQs outside the standard range, and
> adjust the standard range when AIA is available.
>
> Fixes: bb7921cdea12 ("irqchip/riscv-intc: Add support for RISC-V AIA")
> Fixes: e6bd9b966dc8 ("irqchip/riscv-intc: Fix low-level interrupt handler setup for AIA")
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
>
> [...]
Here is the summary with links:
- irqchip/riscv-intc: Fix use of AIA IRQs 32-63 on riscv32
https://git.kernel.org/riscv/c/ca5b0b717b75
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2024-03-25 4:43 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-03-12 21:28 [PATCH] irqchip/riscv-intc: Fix use of AIA IRQs 32-63 on riscv32 Samuel Holland
2024-03-12 21:28 ` Samuel Holland
2024-03-13 4:34 ` Anup Patel
2024-03-13 4:34 ` Anup Patel
2024-03-13 10:55 ` [tip: irq/urgent] irqchip/riscv-intc: Fix use of AIA interrupts " tip-bot2 for Samuel Holland
2024-03-15 18:54 ` tip-bot2 for Samuel Holland
2024-03-25 4:42 ` [PATCH] irqchip/riscv-intc: Fix use of AIA IRQs " patchwork-bot+linux-riscv
2024-03-25 4:42 ` patchwork-bot+linux-riscv
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.