* [PATCH v2] ntb: intel: add GNR support for Intel PCIe gen5 NTB
@ 2022-08-01 20:44 Dave Jiang
2022-08-02 19:52 ` Allen Hubbe
0 siblings, 1 reply; 3+ messages in thread
From: Dave Jiang @ 2022-08-01 20:44 UTC (permalink / raw
To: jdmason; +Cc: allenbh, ntb
Add Intel Granite Rapids NTB PCI device ID and related enabling.
Expectation is same hardware interface as Saphire Rapids Xeon platforms.
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
v2:
- Add debugfs check for GNR generation. Otherwise it fails on GNR.
drivers/ntb/hw/intel/ntb_hw_gen1.c | 6 ++++--
drivers/ntb/hw/intel/ntb_hw_gen4.c | 2 +-
drivers/ntb/hw/intel/ntb_hw_intel.h | 9 +++++++++
3 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/ntb/hw/intel/ntb_hw_gen1.c b/drivers/ntb/hw/intel/ntb_hw_gen1.c
index e5f14e20a9ff..bb928d7b4301 100644
--- a/drivers/ntb/hw/intel/ntb_hw_gen1.c
+++ b/drivers/ntb/hw/intel/ntb_hw_gen1.c
@@ -763,7 +763,7 @@ static ssize_t ndev_debugfs_read(struct file *filp, char __user *ubuf,
return ndev_ntb_debugfs_read(filp, ubuf, count, offp);
else if (pdev_is_gen3(ndev->ntb.pdev))
return ndev_ntb3_debugfs_read(filp, ubuf, count, offp);
- else if (pdev_is_gen4(ndev->ntb.pdev))
+ else if (pdev_is_gen4(ndev->ntb.pdev) || pdev_is_gen5(ndev->ntb.pdev))
return ndev_ntb4_debugfs_read(filp, ubuf, count, offp);
return -ENXIO;
@@ -1874,7 +1874,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
rc = gen3_init_dev(ndev);
if (rc)
goto err_init_dev;
- } else if (pdev_is_gen4(pdev)) {
+ } else if (pdev_is_gen4(pdev) || pdev_is_gen5(pdev)) {
ndev->ntb.ops = &intel_ntb4_ops;
rc = intel_ntb_init_pci(ndev, pdev);
if (rc)
@@ -2047,6 +2047,8 @@ static const struct pci_device_id intel_ntb_pci_tbl[] = {
/* GEN4 */
{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)},
+ /* SPR has same dev id has ICX but different revision id */
+ {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_GNR)},
{0}
};
MODULE_DEVICE_TABLE(pci, intel_ntb_pci_tbl);
diff --git a/drivers/ntb/hw/intel/ntb_hw_gen4.c b/drivers/ntb/hw/intel/ntb_hw_gen4.c
index 4081fc538ff4..22cac7975b3c 100644
--- a/drivers/ntb/hw/intel/ntb_hw_gen4.c
+++ b/drivers/ntb/hw/intel/ntb_hw_gen4.c
@@ -197,7 +197,7 @@ int gen4_init_dev(struct intel_ntb_dev *ndev)
ppd1 = ioread32(ndev->self_mmio + GEN4_PPD1_OFFSET);
if (pdev_is_ICX(pdev))
ndev->ntb.topo = gen4_ppd_topo(ndev, ppd1);
- else if (pdev_is_SPR(pdev))
+ else if (pdev_is_SPR(pdev) || pdev_is_gen5(pdev))
ndev->ntb.topo = spr_ppd_topo(ndev, ppd1);
dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd1,
ntb_topo_string(ndev->ntb.topo));
diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.h b/drivers/ntb/hw/intel/ntb_hw_intel.h
index b233d1c6ba2d..380ec0d8e0d9 100644
--- a/drivers/ntb/hw/intel/ntb_hw_intel.h
+++ b/drivers/ntb/hw/intel/ntb_hw_intel.h
@@ -70,6 +70,8 @@
#define PCI_DEVICE_ID_INTEL_NTB_SS_BDX 0x6F0F
#define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX 0x201C
#define PCI_DEVICE_ID_INTEL_NTB_B2B_ICX 0x347e
+#define PCI_DEVICE_ID_INTEL_NTB_B2B_SPR 0x347e
+#define PCI_DEVICE_ID_INTEL_NTB_B2B_GNR 0x0db4
/* Ntb control and link status */
#define NTB_CTL_CFG_LOCK BIT(0)
@@ -225,7 +227,14 @@ static inline int pdev_is_gen4(struct pci_dev *pdev)
{
if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)
return 1;
+ return 0;
+}
+static inline int pdev_is_gen5(struct pci_dev *pdev)
+{
+ if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_GNR)
+ return 1;
return 0;
}
+
#endif
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2] ntb: intel: add GNR support for Intel PCIe gen5 NTB
2022-08-01 20:44 [PATCH v2] ntb: intel: add GNR support for Intel PCIe gen5 NTB Dave Jiang
@ 2022-08-02 19:52 ` Allen Hubbe
2022-08-02 21:01 ` Dave Jiang
0 siblings, 1 reply; 3+ messages in thread
From: Allen Hubbe @ 2022-08-02 19:52 UTC (permalink / raw
To: Dave Jiang; +Cc: Jon Mason, ntb
On Mon, Aug 1, 2022 at 4:53 PM Dave Jiang <dave.jiang@intel.com> wrote:
> @@ -2047,6 +2047,8 @@ static const struct pci_device_id intel_ntb_pci_tbl[] = {
>
> /* GEN4 */
> {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)},
> + /* SPR has same dev id has ICX but different revision id */
> + {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_GNR)},
comment says SPR but the id is GNR ?
> @@ -70,6 +70,8 @@
> #define PCI_DEVICE_ID_INTEL_NTB_SS_BDX 0x6F0F
> #define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX 0x201C
> #define PCI_DEVICE_ID_INTEL_NTB_B2B_ICX 0x347e
> +#define PCI_DEVICE_ID_INTEL_NTB_B2B_SPR 0x347e
PCI_DEVICE_ID_INTEL_NTB_B2B_SPR is added here, but not used?
pdev_is_SPR(pdev) already exists.
Should that use PCI_DEVICE_ID_INTEL_NTB_B2B_SPR?
> @@ -225,7 +227,14 @@ static inline int pdev_is_gen4(struct pci_dev *pdev)
> {
> if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)
> return 1;
> + return 0;
return pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_ICX;
> +}
>
> +static inline int pdev_is_gen5(struct pci_dev *pdev)
> +{
> + if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_GNR)
> + return 1;
> return 0;
return pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_GNR;
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] ntb: intel: add GNR support for Intel PCIe gen5 NTB
2022-08-02 19:52 ` Allen Hubbe
@ 2022-08-02 21:01 ` Dave Jiang
0 siblings, 0 replies; 3+ messages in thread
From: Dave Jiang @ 2022-08-02 21:01 UTC (permalink / raw
To: Allen Hubbe; +Cc: Jon Mason, ntb
On 8/2/2022 12:52 PM, Allen Hubbe wrote:
> On Mon, Aug 1, 2022 at 4:53 PM Dave Jiang <dave.jiang@intel.com> wrote:
>> @@ -2047,6 +2047,8 @@ static const struct pci_device_id intel_ntb_pci_tbl[] = {
>>
>> /* GEN4 */
>> {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)},
>> + /* SPR has same dev id has ICX but different revision id */
>> + {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_GNR)},
> comment says SPR but the id is GNR ?
The comment is in place of the SPR ID because it's the same as ICX. It's
not the comment for the following GNR id line. The only difference
between ICX and SPR is dev revision ID.
>
>> @@ -70,6 +70,8 @@
>> #define PCI_DEVICE_ID_INTEL_NTB_SS_BDX 0x6F0F
>> #define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX 0x201C
>> #define PCI_DEVICE_ID_INTEL_NTB_B2B_ICX 0x347e
>> +#define PCI_DEVICE_ID_INTEL_NTB_B2B_SPR 0x347e
> PCI_DEVICE_ID_INTEL_NTB_B2B_SPR is added here, but not used?
>
> pdev_is_SPR(pdev) already exists.
> Should that use PCI_DEVICE_ID_INTEL_NTB_B2B_SPR?
Probably, but not for this patch.
>
>> @@ -225,7 +227,14 @@ static inline int pdev_is_gen4(struct pci_dev *pdev)
>> {
>> if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)
>> return 1;
>> + return 0;
> return pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_ICX;
Not a change for this patch. but I'll fix the gen5 function.
>
>> +}
>>
>> +static inline int pdev_is_gen5(struct pci_dev *pdev)
>> +{
>> + if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_GNR)
>> + return 1;
>> return 0;
> return pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_GNR;
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-08-02 21:01 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2022-08-01 20:44 [PATCH v2] ntb: intel: add GNR support for Intel PCIe gen5 NTB Dave Jiang
2022-08-02 19:52 ` Allen Hubbe
2022-08-02 21:01 ` Dave Jiang
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