* [PATCH v7 0/7] Asynchronous flip implementation for i915
@ 2020-09-04 11:33 ` Karthik B S
0 siblings, 0 replies; 19+ messages in thread
From: Karthik B S @ 2020-09-04 11:33 UTC (permalink / raw
To: intel-gfx
Cc: paulo.r.zanoni, michel, Karthik B S, dri-devel, vandita.kulkarni,
uma.shankar, daniel.vetter, nicholas.kazlauskas
Without async flip support in the kernel, fullscreen apps where game
resolution is equal to the screen resolution, must perform an extra blit
per frame prior to flipping.
Asynchronous page flips will also boost the FPS of Mesa benchmarks.
v2: -Few patches have been squashed and patches have been shuffled as
per the reviews on the previous version.
v3: -Few patches have been squashed and patches have been shuffled as
per the reviews on the previous version.
v4: -Made changes to fix the sequence and time stamp issue as per the
comments received on the previous version.
-Timestamps are calculated using the flip done time stamp and current
timestamp. Here I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag is used
for timestamp calculations.
-Event is sent from the interrupt handler immediately using this
updated timestamps and sequence.
-Added more state checks as async flip should only allow change in plane
surface address and nothing else should be allowed to change.
-Added a separate plane hook for async flip.
-Need to find a way to reject fbc enabling if it comes as part of this
flip as bspec states that changes to FBC are not allowed.
v5: -Fixed the Checkpatch and sparse warnings.
v6: -Reverted back to the old timestamping code as per the feedback received.
-Added documentation.
v7: -Changes in intel_atomic_check_async()
-Add vfunc for skl_program_async_surface_address()
Test-with: <20200904102215.4440-1-karthik.b.s@intel.com>
Karthik B S (7):
drm/i915: Add enable/disable flip done and flip done handler
drm/i915: Add support for async flips in I915
drm/i915: Add checks specific to async flips
drm/i915: Do not call drm_crtc_arm_vblank_event in async flips
drm/i915: Add dedicated plane hook for async flip case
Documentation/gpu: Add asynchronous flip documentation for i915
drm/i915: Enable async flips in i915
Documentation/gpu/i915.rst | 6 +
.../gpu/drm/i915/display/intel_atomic_plane.c | 7 +
drivers/gpu/drm/i915/display/intel_display.c | 157 ++++++++++++++++++
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/display/intel_sprite.c | 30 ++++
drivers/gpu/drm/i915/i915_irq.c | 52 ++++++
drivers/gpu/drm/i915/i915_irq.h | 2 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
8 files changed, 258 insertions(+)
--
2.22.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v7 0/7] Asynchronous flip implementation for i915
@ 2020-09-04 11:33 ` Karthik B S
0 siblings, 0 replies; 19+ messages in thread
From: Karthik B S @ 2020-09-04 11:33 UTC (permalink / raw
To: intel-gfx
Cc: paulo.r.zanoni, michel, dri-devel, daniel.vetter, harry.wentland,
nicholas.kazlauskas
Without async flip support in the kernel, fullscreen apps where game
resolution is equal to the screen resolution, must perform an extra blit
per frame prior to flipping.
Asynchronous page flips will also boost the FPS of Mesa benchmarks.
v2: -Few patches have been squashed and patches have been shuffled as
per the reviews on the previous version.
v3: -Few patches have been squashed and patches have been shuffled as
per the reviews on the previous version.
v4: -Made changes to fix the sequence and time stamp issue as per the
comments received on the previous version.
-Timestamps are calculated using the flip done time stamp and current
timestamp. Here I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag is used
for timestamp calculations.
-Event is sent from the interrupt handler immediately using this
updated timestamps and sequence.
-Added more state checks as async flip should only allow change in plane
surface address and nothing else should be allowed to change.
-Added a separate plane hook for async flip.
-Need to find a way to reject fbc enabling if it comes as part of this
flip as bspec states that changes to FBC are not allowed.
v5: -Fixed the Checkpatch and sparse warnings.
v6: -Reverted back to the old timestamping code as per the feedback received.
-Added documentation.
v7: -Changes in intel_atomic_check_async()
-Add vfunc for skl_program_async_surface_address()
Test-with: <20200904102215.4440-1-karthik.b.s@intel.com>
Karthik B S (7):
drm/i915: Add enable/disable flip done and flip done handler
drm/i915: Add support for async flips in I915
drm/i915: Add checks specific to async flips
drm/i915: Do not call drm_crtc_arm_vblank_event in async flips
drm/i915: Add dedicated plane hook for async flip case
Documentation/gpu: Add asynchronous flip documentation for i915
drm/i915: Enable async flips in i915
Documentation/gpu/i915.rst | 6 +
.../gpu/drm/i915/display/intel_atomic_plane.c | 7 +
drivers/gpu/drm/i915/display/intel_display.c | 157 ++++++++++++++++++
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/display/intel_sprite.c | 30 ++++
drivers/gpu/drm/i915/i915_irq.c | 52 ++++++
drivers/gpu/drm/i915/i915_irq.h | 2 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
8 files changed, 258 insertions(+)
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v7 1/7] drm/i915: Add enable/disable flip done and flip done handler
2020-09-04 11:33 ` [Intel-gfx] " Karthik B S
@ 2020-09-04 11:33 ` Karthik B S
-1 siblings, 0 replies; 19+ messages in thread
From: Karthik B S @ 2020-09-04 11:33 UTC (permalink / raw
To: intel-gfx
Cc: paulo.r.zanoni, michel, Karthik B S, dri-devel, vandita.kulkarni,
uma.shankar, daniel.vetter, nicholas.kazlauskas
Add enable/disable flip done functions and the flip done handler
function which handles the flip done interrupt.
Enable the flip done interrupt in IER.
Enable flip done function is called before writing the
surface address register as the write to this register triggers
the flip done interrupt
Flip done handler is used to send the page flip event as soon as the
surface address is written as per the requirement of async flips.
The interrupt is disabled after the event is sent.
v2: -Change function name from icl_* to skl_* (Paulo)
-Move flip handler to this patch (Paulo)
-Remove vblank_put() (Paulo)
-Enable flip done interrupt for gen9+ only (Paulo)
-Enable flip done interrupt in power_well_post_enable hook (Paulo)
-Removed the event check in flip done handler to handle async
flips without pageflip events.
v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
-Make the pending vblank event NULL in the beginning of
flip_done_handler to remove sporadic WARN_ON that is seen.
v4: -Calculate timestamps using flip done time stamp and current
timestamp for async flips (Ville)
v5: -Fix the sparse warning by making the function 'g4x_get_flip_counter'
static.(Reported-by: kernel test robot <lkp@intel.com>)
-Fix the typo in commit message.
v6: -Revert back to old time stamping code.
-Remove the break while calling skl_enable_flip_done. (Paulo)
v7: -Rebased.
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 8 +++
drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++++++++
drivers/gpu/drm/i915/i915_irq.h | 2 +
3 files changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ddb588f863f8..25cea9592891 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15605,6 +15605,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_dbuf_pre_plane_update(state);
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ if (new_crtc_state->uapi.async_flip)
+ skl_enable_flip_done(&crtc->base);
+ }
+
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
dev_priv->display.commit_modeset_enables(state);
@@ -15626,6 +15631,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
drm_atomic_helper_wait_for_flip_done(dev, &state->base);
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ if (new_crtc_state->uapi.async_flip)
+ skl_disable_flip_done(&crtc->base);
+
if (new_crtc_state->hw.active &&
!needs_modeset(new_crtc_state) &&
!new_crtc_state->preload_luts &&
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f113fe44572b..6cc129b031d3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1296,6 +1296,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
u32 crc4) {}
#endif
+static void flip_done_handler(struct drm_i915_private *dev_priv,
+ unsigned int pipe)
+{
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
+ struct drm_crtc_state *crtc_state = crtc->base.state;
+ struct drm_pending_vblank_event *e = crtc_state->event;
+ struct drm_device *dev = &dev_priv->drm;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&dev->event_lock, irqflags);
+
+ crtc_state->event = NULL;
+
+ drm_crtc_send_vblank_event(&crtc->base, e);
+
+ spin_unlock_irqrestore(&dev->event_lock, irqflags);
+}
static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
enum pipe pipe)
@@ -2390,6 +2407,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
if (iir & GEN8_PIPE_VBLANK)
intel_handle_vblank(dev_priv, pipe);
+ if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
+ flip_done_handler(dev_priv, pipe);
+
if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
hsw_pipe_crc_irq_handler(dev_priv, pipe);
@@ -2711,6 +2731,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
return 0;
}
+void skl_enable_flip_done(struct drm_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+
+ bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
+
+ spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+
/* Called from drm generic code, passed 'crtc' which
* we use as a pipe index
*/
@@ -2771,6 +2804,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc)
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
+void skl_disable_flip_done(struct drm_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+
+ bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
+
+ spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+
static void ibx_irq_reset(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = &dev_priv->uncore;
@@ -2981,6 +3027,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
enum pipe pipe;
+ if (INTEL_GEN(dev_priv) >= 9)
+ extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
+
spin_lock_irq(&dev_priv->irq_lock);
if (!intel_irqs_enabled(dev_priv)) {
@@ -3459,6 +3508,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
GEN8_PIPE_FIFO_UNDERRUN;
+ if (INTEL_GEN(dev_priv) >= 9)
+ de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
+
de_port_enables = de_port_masked;
if (IS_GEN9_LP(dev_priv))
de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
index 25f25cd95818..2f10c8135116 100644
--- a/drivers/gpu/drm/i915/i915_irq.h
+++ b/drivers/gpu/drm/i915/i915_irq.h
@@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc);
int i965_enable_vblank(struct drm_crtc *crtc);
int ilk_enable_vblank(struct drm_crtc *crtc);
int bdw_enable_vblank(struct drm_crtc *crtc);
+void skl_enable_flip_done(struct drm_crtc *crtc);
void i8xx_disable_vblank(struct drm_crtc *crtc);
void i915gm_disable_vblank(struct drm_crtc *crtc);
void i965_disable_vblank(struct drm_crtc *crtc);
void ilk_disable_vblank(struct drm_crtc *crtc);
void bdw_disable_vblank(struct drm_crtc *crtc);
+void skl_disable_flip_done(struct drm_crtc *crtc);
void gen2_irq_reset(struct intel_uncore *uncore);
void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
--
2.22.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v7 1/7] drm/i915: Add enable/disable flip done and flip done handler
@ 2020-09-04 11:33 ` Karthik B S
0 siblings, 0 replies; 19+ messages in thread
From: Karthik B S @ 2020-09-04 11:33 UTC (permalink / raw
To: intel-gfx
Cc: paulo.r.zanoni, michel, dri-devel, daniel.vetter, harry.wentland,
nicholas.kazlauskas
Add enable/disable flip done functions and the flip done handler
function which handles the flip done interrupt.
Enable the flip done interrupt in IER.
Enable flip done function is called before writing the
surface address register as the write to this register triggers
the flip done interrupt
Flip done handler is used to send the page flip event as soon as the
surface address is written as per the requirement of async flips.
The interrupt is disabled after the event is sent.
v2: -Change function name from icl_* to skl_* (Paulo)
-Move flip handler to this patch (Paulo)
-Remove vblank_put() (Paulo)
-Enable flip done interrupt for gen9+ only (Paulo)
-Enable flip done interrupt in power_well_post_enable hook (Paulo)
-Removed the event check in flip done handler to handle async
flips without pageflip events.
v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
-Make the pending vblank event NULL in the beginning of
flip_done_handler to remove sporadic WARN_ON that is seen.
v4: -Calculate timestamps using flip done time stamp and current
timestamp for async flips (Ville)
v5: -Fix the sparse warning by making the function 'g4x_get_flip_counter'
static.(Reported-by: kernel test robot <lkp@intel.com>)
-Fix the typo in commit message.
v6: -Revert back to old time stamping code.
-Remove the break while calling skl_enable_flip_done. (Paulo)
v7: -Rebased.
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 8 +++
drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++++++++
drivers/gpu/drm/i915/i915_irq.h | 2 +
3 files changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ddb588f863f8..25cea9592891 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15605,6 +15605,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_dbuf_pre_plane_update(state);
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ if (new_crtc_state->uapi.async_flip)
+ skl_enable_flip_done(&crtc->base);
+ }
+
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
dev_priv->display.commit_modeset_enables(state);
@@ -15626,6 +15631,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
drm_atomic_helper_wait_for_flip_done(dev, &state->base);
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ if (new_crtc_state->uapi.async_flip)
+ skl_disable_flip_done(&crtc->base);
+
if (new_crtc_state->hw.active &&
!needs_modeset(new_crtc_state) &&
!new_crtc_state->preload_luts &&
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f113fe44572b..6cc129b031d3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1296,6 +1296,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
u32 crc4) {}
#endif
+static void flip_done_handler(struct drm_i915_private *dev_priv,
+ unsigned int pipe)
+{
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
+ struct drm_crtc_state *crtc_state = crtc->base.state;
+ struct drm_pending_vblank_event *e = crtc_state->event;
+ struct drm_device *dev = &dev_priv->drm;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&dev->event_lock, irqflags);
+
+ crtc_state->event = NULL;
+
+ drm_crtc_send_vblank_event(&crtc->base, e);
+
+ spin_unlock_irqrestore(&dev->event_lock, irqflags);
+}
static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
enum pipe pipe)
@@ -2390,6 +2407,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
if (iir & GEN8_PIPE_VBLANK)
intel_handle_vblank(dev_priv, pipe);
+ if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
+ flip_done_handler(dev_priv, pipe);
+
if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
hsw_pipe_crc_irq_handler(dev_priv, pipe);
@@ -2711,6 +2731,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
return 0;
}
+void skl_enable_flip_done(struct drm_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+
+ bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
+
+ spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+
/* Called from drm generic code, passed 'crtc' which
* we use as a pipe index
*/
@@ -2771,6 +2804,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc)
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
+void skl_disable_flip_done(struct drm_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+
+ bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
+
+ spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+
static void ibx_irq_reset(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = &dev_priv->uncore;
@@ -2981,6 +3027,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
enum pipe pipe;
+ if (INTEL_GEN(dev_priv) >= 9)
+ extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
+
spin_lock_irq(&dev_priv->irq_lock);
if (!intel_irqs_enabled(dev_priv)) {
@@ -3459,6 +3508,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
GEN8_PIPE_FIFO_UNDERRUN;
+ if (INTEL_GEN(dev_priv) >= 9)
+ de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
+
de_port_enables = de_port_masked;
if (IS_GEN9_LP(dev_priv))
de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
index 25f25cd95818..2f10c8135116 100644
--- a/drivers/gpu/drm/i915/i915_irq.h
+++ b/drivers/gpu/drm/i915/i915_irq.h
@@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc);
int i965_enable_vblank(struct drm_crtc *crtc);
int ilk_enable_vblank(struct drm_crtc *crtc);
int bdw_enable_vblank(struct drm_crtc *crtc);
+void skl_enable_flip_done(struct drm_crtc *crtc);
void i8xx_disable_vblank(struct drm_crtc *crtc);
void i915gm_disable_vblank(struct drm_crtc *crtc);
void i965_disable_vblank(struct drm_crtc *crtc);
void ilk_disable_vblank(struct drm_crtc *crtc);
void bdw_disable_vblank(struct drm_crtc *crtc);
+void skl_disable_flip_done(struct drm_crtc *crtc);
void gen2_irq_reset(struct intel_uncore *uncore);
void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v7 2/7] drm/i915: Add support for async flips in I915
2020-09-04 11:33 ` [Intel-gfx] " Karthik B S
@ 2020-09-04 11:33 ` Karthik B S
-1 siblings, 0 replies; 19+ messages in thread
From: Karthik B S @ 2020-09-04 11:33 UTC (permalink / raw
To: intel-gfx
Cc: paulo.r.zanoni, michel, Karthik B S, dri-devel, vandita.kulkarni,
uma.shankar, daniel.vetter, nicholas.kazlauskas
Set the Async Address Update Enable bit in plane ctl
when async flip is requested.
v2: -Move the Async flip enablement to individual patch (Paulo)
v3: -Rebased.
v4: -Add separate plane hook for async flip case (Ville)
v5: -Rebased.
v6: -Move the plane hook to separate patch. (Paulo)
-Remove the early return in skl_plane_ctl. (Paulo)
v7: -Move async address update enable to skl_plane_ctl_crtc() (Ville)
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 25cea9592891..c795ea01cec3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4784,6 +4784,9 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
u32 plane_ctl = 0;
+ if (crtc_state->uapi.async_flip)
+ plane_ctl |= PLANE_CTL_ASYNC_FLIP;
+
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
return plane_ctl;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ab4b1abd4364..abf43e63264c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6924,6 +6924,7 @@ enum {
#define PLANE_CTL_TILED_X (1 << 10)
#define PLANE_CTL_TILED_Y (4 << 10)
#define PLANE_CTL_TILED_YF (5 << 10)
+#define PLANE_CTL_ASYNC_FLIP (1 << 9)
#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
--
2.22.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v7 2/7] drm/i915: Add support for async flips in I915
@ 2020-09-04 11:33 ` Karthik B S
0 siblings, 0 replies; 19+ messages in thread
From: Karthik B S @ 2020-09-04 11:33 UTC (permalink / raw
To: intel-gfx
Cc: paulo.r.zanoni, michel, dri-devel, daniel.vetter, harry.wentland,
nicholas.kazlauskas
Set the Async Address Update Enable bit in plane ctl
when async flip is requested.
v2: -Move the Async flip enablement to individual patch (Paulo)
v3: -Rebased.
v4: -Add separate plane hook for async flip case (Ville)
v5: -Rebased.
v6: -Move the plane hook to separate patch. (Paulo)
-Remove the early return in skl_plane_ctl. (Paulo)
v7: -Move async address update enable to skl_plane_ctl_crtc() (Ville)
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 25cea9592891..c795ea01cec3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4784,6 +4784,9 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
u32 plane_ctl = 0;
+ if (crtc_state->uapi.async_flip)
+ plane_ctl |= PLANE_CTL_ASYNC_FLIP;
+
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
return plane_ctl;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ab4b1abd4364..abf43e63264c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6924,6 +6924,7 @@ enum {
#define PLANE_CTL_TILED_X (1 << 10)
#define PLANE_CTL_TILED_Y (4 << 10)
#define PLANE_CTL_TILED_YF (5 << 10)
+#define PLANE_CTL_ASYNC_FLIP (1 << 9)
#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v7 3/7] drm/i915: Add checks specific to async flips
2020-09-04 11:33 ` [Intel-gfx] " Karthik B S
@ 2020-09-04 11:33 ` Karthik B S
-1 siblings, 0 replies; 19+ messages in thread
From: Karthik B S @ 2020-09-04 11:33 UTC (permalink / raw
To: intel-gfx
Cc: paulo.r.zanoni, michel, Karthik B S, dri-devel, vandita.kulkarni,
uma.shankar, daniel.vetter, nicholas.kazlauskas
If flip is requested on any other plane, reject it.
Make sure there is no change in fbc, offset and framebuffer modifiers
when async flip is requested.
If any of these are modified, reject async flip.
v2: -Replace DRM_ERROR (Paulo)
-Add check for changes in OFFSET, FBC, RC(Paulo)
v3: -Removed TODO as benchmarking tests have been run now.
v4: -Added more state checks for async flip (Ville)
-Moved intel_atomic_check_async to the end of intel_atomic_check
as the plane checks needs to pass before this. (Ville)
-Removed crtc_state->enable_fbc check. (Ville)
-Set the I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag for async
flip case as scanline counter is not reliable here.
v5: -Fix typo and other check patch errors seen in CI
in 'intel_atomic_check_async' function.
v6: -Don't call intel_atomic_check_async multiple times. (Ville)
-Remove the check for n_planes in intel_atomic_check_async
-Added documentation for async flips. (Paulo)
v7: -Replace 'intel_plane' with 'plane'. (Ville)
-Replace all uapi.foo as hw.foo. (Ville)
-Do not use intel_wm_need_update function. (Ville)
-Add destination coordinate check. (Ville)
-Do not allow async flip with linear buffer
on older hw as it has issues with this. (Ville)
-Remove break after intel_atomic_check_async. (Ville)
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 143 +++++++++++++++++++
1 file changed, 143 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c795ea01cec3..6fa142b1c6ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14875,6 +14875,142 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
return false;
}
+/**
+ * DOC: asynchronous flip implementation
+ *
+ * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
+ * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
+ * Correspondingly, support is currently added for primary plane only.
+ *
+ * Async flip can only change the plane surface address, so anything else
+ * changing is rejected from the intel_atomic_check_async() function.
+ * Once this check is cleared, flip done interrupt is enabled using
+ * the skl_enable_flip_done() function.
+ *
+ * As soon as the surface address register is written, flip done interrupt is
+ * generated and the requested events are sent to the usersapce in the interrupt
+ * handler itself. The timestamp and sequence sent during the flip done event
+ * correspond to the last vblank and have no relation to the actual time when
+ * the flip done event was sent.
+ */
+
+static int intel_atomic_check_async(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc_state *old_crtc_state, *new_crtc_state;
+ struct intel_plane_state *new_plane_state, *old_plane_state;
+ struct intel_crtc *crtc;
+ struct intel_plane *plane;
+ int i;
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ if (needs_modeset(new_crtc_state)) {
+ DRM_DEBUG_KMS("Modeset Required. Async flip not supported\n");
+ return -EINVAL;
+ }
+
+ if (!new_crtc_state->hw.active) {
+ DRM_DEBUG_KMS("CRTC inactive\n");
+ return -EINVAL;
+ }
+ if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
+ DRM_DEBUG_KMS("Active planes cannot be changed during async flip\n");
+ return -EINVAL;
+ }
+ }
+
+ for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
+ new_plane_state, i) {
+ /*TODO: Async flip is only supported through the page flip IOCTL
+ * as of now. So support currently added for primary plane only.
+ * Support for other planes should be added when async flip is
+ * enabled in the atomic IOCTL path.
+ */
+ if (plane->id != PLANE_PRIMARY)
+ return -EINVAL;
+
+ /*FIXME: This check is kept generic for all gen <= 10 platforms.
+ * Need to verify this for all gen9 and gen10 platforms to enable
+ * this selectively if required.
+ */
+ if (new_plane_state->hw.fb->modifier == DRM_FORMAT_MOD_LINEAR &&
+ INTEL_GEN(dev_priv) <= 10) {
+ DRM_DEBUG_KMS("Linear memory does not support async flips on gen <= 10\n");
+ return -EINVAL;
+ }
+
+ if (old_plane_state->color_plane[0].x !=
+ new_plane_state->color_plane[0].x ||
+ old_plane_state->color_plane[0].y !=
+ new_plane_state->color_plane[0].y) {
+ DRM_DEBUG_KMS("Offsets cannot be changed in async flip\n");
+ return -EINVAL;
+ }
+
+ if (old_plane_state->hw.fb->modifier !=
+ new_plane_state->hw.fb->modifier) {
+ DRM_DEBUG_KMS("Framebuffer modifiers cannot be changed in async flip\n");
+ return -EINVAL;
+ }
+
+ if (old_plane_state->hw.fb->format !=
+ new_plane_state->hw.fb->format) {
+ DRM_DEBUG_KMS("Framebuffer format cannot be changed in async flip\n");
+ return -EINVAL;
+ }
+
+ if (old_plane_state->hw.rotation !=
+ new_plane_state->hw.rotation) {
+ DRM_DEBUG_KMS("Rotation cannot be changed in async flip\n");
+ return -EINVAL;
+ }
+
+ if (old_plane_state->hw.fb->width !=
+ new_plane_state->hw.fb->width ||
+ old_plane_state->hw.fb->height !=
+ new_plane_state->hw.fb->height) {
+ DRM_DEBUG_KMS("Framebuffer dimensions cannot be changed in async flip\n");
+ return -EINVAL;
+ }
+
+ if (old_plane_state->uapi.src_w != new_plane_state->uapi.src_w ||
+ old_plane_state->uapi.src_h != new_plane_state->uapi.src_h ||
+ old_plane_state->uapi.src_x != new_plane_state->uapi.src_x ||
+ old_plane_state->uapi.src_y != new_plane_state->uapi.src_y ||
+ old_plane_state->uapi.crtc_w != new_plane_state->uapi.crtc_w ||
+ old_plane_state->uapi.crtc_h != new_plane_state->uapi.crtc_h ||
+ old_plane_state->uapi.crtc_x != new_plane_state->uapi.crtc_x ||
+ old_plane_state->uapi.crtc_y != new_plane_state->uapi.crtc_y) {
+ DRM_DEBUG_KMS("Plane size/co-ordinates cannot be changed in async flip\n");
+ return -EINVAL;
+ }
+
+ if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
+ DRM_DEBUG_KMS("Alpha value cannot be changed in async flip\n");
+ return -EINVAL;
+ }
+
+ if (old_plane_state->hw.pixel_blend_mode !=
+ new_plane_state->hw.pixel_blend_mode) {
+ DRM_DEBUG_KMS("Pixel blend mode cannot be changed in async flip\n");
+ return -EINVAL;
+ }
+
+ if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
+ DRM_DEBUG_KMS("Color encoding cannot be changed in async flip\n");
+ return -EINVAL;
+ }
+
+ if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
+ DRM_DEBUG_KMS("Color range cannot be changed in async flip\n");
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
/**
* intel_atomic_check - validate state object
* @dev: drm device
@@ -15052,6 +15188,13 @@ static int intel_atomic_check(struct drm_device *dev,
"[modeset]" : "[fastset]");
}
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ if (new_crtc_state->uapi.async_flip) {
+ ret = intel_atomic_check_async(state);
+ if (ret)
+ goto fail;
+ }
+ }
return 0;
fail:
--
2.22.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v7 3/7] drm/i915: Add checks specific to async flips
@ 2020-09-04 11:33 ` Karthik B S
0 siblings, 0 replies; 19+ messages in thread
From: Karthik B S @ 2020-09-04 11:33 UTC (permalink / raw
To: intel-gfx
Cc: paulo.r.zanoni, michel, dri-devel, daniel.vetter, harry.wentland,
nicholas.kazlauskas
If flip is requested on any other plane, reject it.
Make sure there is no change in fbc, offset and framebuffer modifiers
when async flip is requested.
If any of these are modified, reject async flip.
v2: -Replace DRM_ERROR (Paulo)
-Add check for changes in OFFSET, FBC, RC(Paulo)
v3: -Removed TODO as benchmarking tests have been run now.
v4: -Added more state checks for async flip (Ville)
-Moved intel_atomic_check_async to the end of intel_atomic_check
as the plane checks needs to pass before this. (Ville)
-Removed crtc_state->enable_fbc check. (Ville)
-Set the I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag for async
flip case as scanline counter is not reliable here.
v5: -Fix typo and other check patch errors seen in CI
in 'intel_atomic_check_async' function.
v6: -Don't call intel_atomic_check_async multiple times. (Ville)
-Remove the check for n_planes in intel_atomic_check_async
-Added documentation for async flips. (Paulo)
v7: -Replace 'intel_plane' with 'plane'. (Ville)
-Replace all uapi.foo as hw.foo. (Ville)
-Do not use intel_wm_need_update function. (Ville)
-Add destination coordinate check. (Ville)
-Do not allow async flip with linear buffer
on older hw as it has issues with this. (Ville)
-Remove break after intel_atomic_check_async. (Ville)
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 143 +++++++++++++++++++
1 file changed, 143 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c795ea01cec3..6fa142b1c6ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14875,6 +14875,142 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
return false;
}
+/**
+ * DOC: asynchronous flip implementation
+ *
+ * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
+ * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
+ * Correspondingly, support is currently added for primary plane only.
+ *
+ * Async flip can only change the plane surface address, so anything else
+ * changing is rejected from the intel_atomic_check_async() function.
+ * Once this check is cleared, flip done interrupt is enabled using
+ * the skl_enable_flip_done() function.
+ *
+ * As soon as the surface address register is written, flip done interrupt is
+ * generated and the requested events are sent to the usersapce in the interrupt
+ * handler itself. The timestamp and sequence sent during the flip done event
+ * correspond to the last vblank and have no relation to the actual time when
+ * the flip done event was sent.
+ */
+
+static int intel_atomic_check_async(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc_state *old_crtc_state, *new_crtc_state;
+ struct intel_plane_state *new_plane_state, *old_plane_state;
+ struct intel_crtc *crtc;
+ struct intel_plane *plane;
+ int i;
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ if (needs_modeset(new_crtc_state)) {
+ DRM_DEBUG_KMS("Modeset Required. Async flip not supported\n");
+ return -EINVAL;
+ }
+
+ if (!new_crtc_state->hw.active) {
+ DRM_DEBUG_KMS("CRTC inactive\n");
+ return -EINVAL;
+ }
+ if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
+ DRM_DEBUG_KMS("Active planes cannot be changed during async flip\n");
+ return -EINVAL;
+ }
+ }
+
+ for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
+ new_plane_state, i) {
+ /*TODO: Async flip is only supported through the page flip IOCTL
+ * as of now. So support currently added for primary plane only.
+ * Support for other planes should be added when async flip is
+ * enabled in the atomic IOCTL path.
+ */
+ if (plane->id != PLANE_PRIMARY)
+ return -EINVAL;
+
+ /*FIXME: This check is kept generic for all gen <= 10 platforms.
+ * Need to verify this for all gen9 and gen10 platforms to enable
+ * this selectively if required.
+ */
+ if (new_plane_state->hw.fb->modifier == DRM_FORMAT_MOD_LINEAR &&
+ INTEL_GEN(dev_priv) <= 10) {
+ DRM_DEBUG_KMS("Linear memory does not support async flips on gen <= 10\n");
+ return -EINVAL;
+ }
+
+ if (old_plane_state->color_plane[0].x !=
+ new_plane_state->color_plane[0].x ||
+ old_plane_state->color_plane[0].y !=
+ new_plane_state->color_plane[0].y) {
+ DRM_DEBUG_KMS("Offsets cannot be changed in async flip\n");
+ return -EINVAL;
+ }
+
+ if (old_plane_state->hw.fb->modifier !=
+ new_plane_state->hw.fb->modifier) {
+ DRM_DEBUG_KMS("Framebuffer modifiers cannot be changed in async flip\n");
+ return -EINVAL;
+ }
+
+ if (old_plane_state->hw.fb->format !=
+ new_plane_state->hw.fb->format) {
+ DRM_DEBUG_KMS("Framebuffer format cannot be changed in async flip\n");
+ return -EINVAL;
+ }
+
+ if (old_plane_state->hw.rotation !=
+ new_plane_state->hw.rotation) {
+ DRM_DEBUG_KMS("Rotation cannot be changed in async flip\n");
+ return -EINVAL;
+ }
+
+ if (old_plane_state->hw.fb->width !=
+ new_plane_state->hw.fb->width ||
+ old_plane_state->hw.fb->height !=
+ new_plane_state->hw.fb->height) {
+ DRM_DEBUG_KMS("Framebuffer dimensions cannot be changed in async flip\n");
+ return -EINVAL;
+ }
+
+ if (old_plane_state->uapi.src_w != new_plane_state->uapi.src_w ||
+ old_plane_state->uapi.src_h != new_plane_state->uapi.src_h ||
+ old_plane_state->uapi.src_x != new_plane_state->uapi.src_x ||
+ old_plane_state->uapi.src_y != new_plane_state->uapi.src_y ||
+ old_plane_state->uapi.crtc_w != new_plane_state->uapi.crtc_w ||
+ old_plane_state->uapi.crtc_h != new_plane_state->uapi.crtc_h ||
+ old_plane_state->uapi.crtc_x != new_plane_state->uapi.crtc_x ||
+ old_plane_state->uapi.crtc_y != new_plane_state->uapi.crtc_y) {
+ DRM_DEBUG_KMS("Plane size/co-ordinates cannot be changed in async flip\n");
+ return -EINVAL;
+ }
+
+ if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
+ DRM_DEBUG_KMS("Alpha value cannot be changed in async flip\n");
+ return -EINVAL;
+ }
+
+ if (old_plane_state->hw.pixel_blend_mode !=
+ new_plane_state->hw.pixel_blend_mode) {
+ DRM_DEBUG_KMS("Pixel blend mode cannot be changed in async flip\n");
+ return -EINVAL;
+ }
+
+ if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
+ DRM_DEBUG_KMS("Color encoding cannot be changed in async flip\n");
+ return -EINVAL;
+ }
+
+ if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
+ DRM_DEBUG_KMS("Color range cannot be changed in async flip\n");
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
/**
* intel_atomic_check - validate state object
* @dev: drm device
@@ -15052,6 +15188,13 @@ static int intel_atomic_check(struct drm_device *dev,
"[modeset]" : "[fastset]");
}
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ if (new_crtc_state->uapi.async_flip) {
+ ret = intel_atomic_check_async(state);
+ if (ret)
+ goto fail;
+ }
+ }
return 0;
fail:
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v7 4/7] drm/i915: Do not call drm_crtc_arm_vblank_event in async flips
2020-09-04 11:33 ` [Intel-gfx] " Karthik B S
@ 2020-09-04 11:33 ` Karthik B S
-1 siblings, 0 replies; 19+ messages in thread
From: Karthik B S @ 2020-09-04 11:33 UTC (permalink / raw
To: intel-gfx
Cc: paulo.r.zanoni, michel, Karthik B S, dri-devel, vandita.kulkarni,
uma.shankar, daniel.vetter, nicholas.kazlauskas
Since the flip done event will be sent in the flip_done_handler,
no need to add the event to the list and delay it for later.
v2: -Moved the async check above vblank_get as it
was causing issues for PSR.
v3: -No need to wait for vblank to pass, as this wait was causing a
16ms delay once every few flips.
v4: -Rebased.
v5: -Rebased.
v6: -Rebased.
v7: -No need of irq disable if we are not doing vblank evade. (Ville)
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 5ac0dbf0e03d..f0c89418d2e1 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -93,6 +93,9 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
DEFINE_WAIT(wait);
u32 psr_status;
+ if (new_crtc_state->uapi.async_flip)
+ return;
+
vblank_start = adjusted_mode->crtc_vblank_start;
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
vblank_start = DIV_ROUND_UP(vblank_start, 2);
@@ -202,6 +205,9 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
+ if (new_crtc_state->uapi.async_flip)
+ return;
+
/* We're still in the vblank-evade critical section, this can't race.
* Would be slightly nice to just grab the vblank count and arm the
* event outside of the critical section - the spinlock might spin for a
--
2.22.0
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v7 4/7] drm/i915: Do not call drm_crtc_arm_vblank_event in async flips
@ 2020-09-04 11:33 ` Karthik B S
0 siblings, 0 replies; 19+ messages in thread
From: Karthik B S @ 2020-09-04 11:33 UTC (permalink / raw
To: intel-gfx
Cc: paulo.r.zanoni, michel, dri-devel, daniel.vetter, harry.wentland,
nicholas.kazlauskas
Since the flip done event will be sent in the flip_done_handler,
no need to add the event to the list and delay it for later.
v2: -Moved the async check above vblank_get as it
was causing issues for PSR.
v3: -No need to wait for vblank to pass, as this wait was causing a
16ms delay once every few flips.
v4: -Rebased.
v5: -Rebased.
v6: -Rebased.
v7: -No need of irq disable if we are not doing vblank evade. (Ville)
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 5ac0dbf0e03d..f0c89418d2e1 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -93,6 +93,9 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
DEFINE_WAIT(wait);
u32 psr_status;
+ if (new_crtc_state->uapi.async_flip)
+ return;
+
vblank_start = adjusted_mode->crtc_vblank_start;
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
vblank_start = DIV_ROUND_UP(vblank_start, 2);
@@ -202,6 +205,9 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
+ if (new_crtc_state->uapi.async_flip)
+ return;
+
/* We're still in the vblank-evade critical section, this can't race.
* Would be slightly nice to just grab the vblank count and arm the
* event outside of the critical section - the spinlock might spin for a
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v7 5/7] drm/i915: Add dedicated plane hook for async flip case
2020-09-04 11:33 ` [Intel-gfx] " Karthik B S
@ 2020-09-04 11:33 ` Karthik B S
-1 siblings, 0 replies; 19+ messages in thread
From: Karthik B S @ 2020-09-04 11:33 UTC (permalink / raw
To: intel-gfx
Cc: paulo.r.zanoni, michel, Karthik B S, dri-devel, vandita.kulkarni,
uma.shankar, daniel.vetter, nicholas.kazlauskas
This hook is added to avoid writing other plane registers in case of
async flips, so that we do not write the double buffered registers
during async surface address update.
v7: -Plane ctl needs bits from skl_plane_ctl_crtc as well. (Ville)
-Add a vfunc for skl_program_async_surface_address
and call it from intel_update_plane. (Ville)
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 7 ++++++
.../drm/i915/display/intel_display_types.h | 3 +++
drivers/gpu/drm/i915/display/intel_sprite.c | 24 +++++++++++++++++++
3 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 79032701873a..fdc633020255 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -408,6 +408,13 @@ void intel_update_plane(struct intel_plane *plane,
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
trace_intel_update_plane(&plane->base, crtc);
+
+ if (crtc_state->uapi.async_flip) {
+ plane->program_async_surface_address(plane,
+ crtc_state, plane_state);
+ return;
+ }
+
plane->update_plane(plane, crtc_state, plane_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 413b60337a0b..b61b7207d79f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1188,6 +1188,9 @@ struct intel_plane {
struct intel_plane_state *plane_state);
int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
+ void (*program_async_surface_address)(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state);
};
struct intel_watermark_params {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index f0c89418d2e1..69407dfcebf6 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -609,6 +609,29 @@ icl_program_input_csc(struct intel_plane *plane,
PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
}
+static void
+skl_program_async_surface_address(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ unsigned long irqflags;
+ enum plane_id plane_id = plane->id;
+ enum pipe pipe = plane->pipe;
+ u32 surf_addr = plane_state->color_plane[0].offset;
+ u32 plane_ctl = plane_state->ctl;
+
+ plane_ctl |= skl_plane_ctl_crtc(crtc_state);
+
+ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+
+ intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
+ intel_plane_ggtt_offset(plane_state) + surf_addr);
+
+ spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
+
static void
skl_program_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -3096,6 +3119,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane->get_hw_state = skl_plane_get_hw_state;
plane->check_plane = skl_plane_check;
plane->min_cdclk = skl_plane_min_cdclk;
+ plane->program_async_surface_address = skl_program_async_surface_address;
if (INTEL_GEN(dev_priv) >= 11)
formats = icl_get_plane_formats(dev_priv, pipe,
--
2.22.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v7 5/7] drm/i915: Add dedicated plane hook for async flip case
@ 2020-09-04 11:33 ` Karthik B S
0 siblings, 0 replies; 19+ messages in thread
From: Karthik B S @ 2020-09-04 11:33 UTC (permalink / raw
To: intel-gfx
Cc: paulo.r.zanoni, michel, dri-devel, daniel.vetter, harry.wentland,
nicholas.kazlauskas
This hook is added to avoid writing other plane registers in case of
async flips, so that we do not write the double buffered registers
during async surface address update.
v7: -Plane ctl needs bits from skl_plane_ctl_crtc as well. (Ville)
-Add a vfunc for skl_program_async_surface_address
and call it from intel_update_plane. (Ville)
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 7 ++++++
.../drm/i915/display/intel_display_types.h | 3 +++
drivers/gpu/drm/i915/display/intel_sprite.c | 24 +++++++++++++++++++
3 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 79032701873a..fdc633020255 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -408,6 +408,13 @@ void intel_update_plane(struct intel_plane *plane,
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
trace_intel_update_plane(&plane->base, crtc);
+
+ if (crtc_state->uapi.async_flip) {
+ plane->program_async_surface_address(plane,
+ crtc_state, plane_state);
+ return;
+ }
+
plane->update_plane(plane, crtc_state, plane_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 413b60337a0b..b61b7207d79f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1188,6 +1188,9 @@ struct intel_plane {
struct intel_plane_state *plane_state);
int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
+ void (*program_async_surface_address)(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state);
};
struct intel_watermark_params {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index f0c89418d2e1..69407dfcebf6 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -609,6 +609,29 @@ icl_program_input_csc(struct intel_plane *plane,
PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
}
+static void
+skl_program_async_surface_address(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ unsigned long irqflags;
+ enum plane_id plane_id = plane->id;
+ enum pipe pipe = plane->pipe;
+ u32 surf_addr = plane_state->color_plane[0].offset;
+ u32 plane_ctl = plane_state->ctl;
+
+ plane_ctl |= skl_plane_ctl_crtc(crtc_state);
+
+ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+
+ intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
+ intel_plane_ggtt_offset(plane_state) + surf_addr);
+
+ spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
+
static void
skl_program_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -3096,6 +3119,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane->get_hw_state = skl_plane_get_hw_state;
plane->check_plane = skl_plane_check;
plane->min_cdclk = skl_plane_min_cdclk;
+ plane->program_async_surface_address = skl_program_async_surface_address;
if (INTEL_GEN(dev_priv) >= 11)
formats = icl_get_plane_formats(dev_priv, pipe,
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v7 6/7] Documentation/gpu: Add asynchronous flip documentation for i915
2020-09-04 11:33 ` [Intel-gfx] " Karthik B S
@ 2020-09-04 11:33 ` Karthik B S
-1 siblings, 0 replies; 19+ messages in thread
From: Karthik B S @ 2020-09-04 11:33 UTC (permalink / raw
To: intel-gfx
Cc: paulo.r.zanoni, michel, Karthik B S, dri-devel, vandita.kulkarni,
uma.shankar, daniel.vetter, nicholas.kazlauskas
Add the details of the implementation of asynchronous flips for i915.
v7: -Rebased.
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
Documentation/gpu/i915.rst | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 33cc6ddf8f64..84ead508f7ad 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -118,6 +118,12 @@ Atomic Plane Helpers
.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c
:internal:
+Asynchronous Page Flip
+----------------------
+
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c
+ :doc: asynchronous flip implementation
+
Output Probing
--------------
--
2.22.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v7 6/7] Documentation/gpu: Add asynchronous flip documentation for i915
@ 2020-09-04 11:33 ` Karthik B S
0 siblings, 0 replies; 19+ messages in thread
From: Karthik B S @ 2020-09-04 11:33 UTC (permalink / raw
To: intel-gfx
Cc: paulo.r.zanoni, michel, dri-devel, daniel.vetter, harry.wentland,
nicholas.kazlauskas
Add the details of the implementation of asynchronous flips for i915.
v7: -Rebased.
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
Documentation/gpu/i915.rst | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 33cc6ddf8f64..84ead508f7ad 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -118,6 +118,12 @@ Atomic Plane Helpers
.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c
:internal:
+Asynchronous Page Flip
+----------------------
+
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c
+ :doc: asynchronous flip implementation
+
Output Probing
--------------
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v7 7/7] drm/i915: Enable async flips in i915
2020-09-04 11:33 ` [Intel-gfx] " Karthik B S
@ 2020-09-04 11:33 ` Karthik B S
-1 siblings, 0 replies; 19+ messages in thread
From: Karthik B S @ 2020-09-04 11:33 UTC (permalink / raw
To: intel-gfx
Cc: paulo.r.zanoni, michel, Karthik B S, dri-devel, vandita.kulkarni,
uma.shankar, daniel.vetter, nicholas.kazlauskas
Enable asynchronous flips in i915 for gen9+ platforms.
v2: -Async flip enablement should be a stand alone patch (Paulo)
v3: -Move the patch to the end of the serires (Paulo)
v4: -Rebased.
v5: -Rebased.
v6: -Rebased.
v7: -Rebased.
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6fa142b1c6ff..854413973637 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17974,6 +17974,9 @@ static void intel_mode_config_init(struct drm_i915_private *i915)
mode_config->funcs = &intel_mode_funcs;
+ if (INTEL_GEN(i915) >= 9)
+ mode_config->async_page_flip = true;
+
/*
* Maximum framebuffer dimensions, chosen to match
* the maximum render engine surface size on gen4+.
--
2.22.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v7 7/7] drm/i915: Enable async flips in i915
@ 2020-09-04 11:33 ` Karthik B S
0 siblings, 0 replies; 19+ messages in thread
From: Karthik B S @ 2020-09-04 11:33 UTC (permalink / raw
To: intel-gfx
Cc: paulo.r.zanoni, michel, dri-devel, daniel.vetter, harry.wentland,
nicholas.kazlauskas
Enable asynchronous flips in i915 for gen9+ platforms.
v2: -Async flip enablement should be a stand alone patch (Paulo)
v3: -Move the patch to the end of the serires (Paulo)
v4: -Rebased.
v5: -Rebased.
v6: -Rebased.
v7: -Rebased.
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6fa142b1c6ff..854413973637 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17974,6 +17974,9 @@ static void intel_mode_config_init(struct drm_i915_private *i915)
mode_config->funcs = &intel_mode_funcs;
+ if (INTEL_GEN(i915) >= 9)
+ mode_config->async_page_flip = true;
+
/*
* Maximum framebuffer dimensions, chosen to match
* the maximum render engine surface size on gen4+.
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Asynchronous flip implementation for i915 (rev7)
2020-09-04 11:33 ` [Intel-gfx] " Karthik B S
` (7 preceding siblings ...)
(?)
@ 2020-09-04 13:45 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2020-09-04 13:45 UTC (permalink / raw
To: Karthik B S; +Cc: intel-gfx
== Series Details ==
Series: Asynchronous flip implementation for i915 (rev7)
URL : https://patchwork.freedesktop.org/series/74386/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1311:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216
+./include/linux/seqlock.h:752:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:778:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Asynchronous flip implementation for i915 (rev7)
2020-09-04 11:33 ` [Intel-gfx] " Karthik B S
` (8 preceding siblings ...)
(?)
@ 2020-09-04 14:01 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2020-09-04 14:01 UTC (permalink / raw
To: Karthik B S; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 5260 bytes --]
== Series Details ==
Series: Asynchronous flip implementation for i915 (rev7)
URL : https://patchwork.freedesktop.org/series/74386/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8965 -> Patchwork_18443
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/index.html
Known issues
------------
Here are the changes found in Patchwork_18443 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload:
- fi-bxt-dsi: [PASS][1] -> [DMESG-WARN][2] ([i915#1635] / [i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/fi-bxt-dsi/igt@i915_module_load@reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/fi-bxt-dsi/igt@i915_module_load@reload.html
* igt@i915_selftest@live@execlists:
- fi-icl-y: [PASS][3] -> [INCOMPLETE][4] ([i915#2276])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/fi-icl-y/igt@i915_selftest@live@execlists.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/fi-icl-y/igt@i915_selftest@live@execlists.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [PASS][5] -> [FAIL][6] ([i915#262])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-kefka: [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
#### Possible fixes ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- {fi-kbl-7560u}: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
#### Warnings ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [SKIP][15] ([fdo#109271]) -> [DMESG-WARN][16] ([i915#2203])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#2276]: https://gitlab.freedesktop.org/drm/intel/issues/2276
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
Participating hosts (36 -> 33)
------------------------------
Missing (3): fi-byt-clapper fi-byt-squawks fi-bsw-cyan
Build changes
-------------
* IGT: IGT_5778 -> IGTPW_4951
* Linux: CI_DRM_8965 -> Patchwork_18443
CI-20190529: 20190529
CI_DRM_8965: f4cbf17fababf80c1c67c6f1687fb8bf7e00a263 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_4951: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4951/index.html
IGT_5778: 9a9db93fd2f2f59eb37b79d4b9a623067a945bac @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18443: 521ae51c4363f49a4a1a4cc47614f0bd2f8c8ca2 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
521ae51c4363 drm/i915: Enable async flips in i915
addeff0ae8dd Documentation/gpu: Add asynchronous flip documentation for i915
ce84530e252e drm/i915: Add dedicated plane hook for async flip case
eac670b8dfb8 drm/i915: Do not call drm_crtc_arm_vblank_event in async flips
d22c29a8190f drm/i915: Add checks specific to async flips
3f60d1175525 drm/i915: Add support for async flips in I915
dba432872ad3 drm/i915: Add enable/disable flip done and flip done handler
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/index.html
[-- Attachment #1.2: Type: text/html, Size: 6373 bytes --]
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Asynchronous flip implementation for i915 (rev7)
2020-09-04 11:33 ` [Intel-gfx] " Karthik B S
` (9 preceding siblings ...)
(?)
@ 2020-09-05 0:10 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2020-09-05 0:10 UTC (permalink / raw
To: Karthik B S; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 24100 bytes --]
== Series Details ==
Series: Asynchronous flip implementation for i915 (rev7)
URL : https://patchwork.freedesktop.org/series/74386/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8965_full -> Patchwork_18443_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18443_full:
### IGT changes ###
#### Possible regressions ####
* {igt@kms_async_flips@alternate-sync-async-flip} (NEW):
- shard-iclb: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-iclb4/igt@kms_async_flips@alternate-sync-async-flip.html
* {igt@kms_async_flips@async-flip-with-page-flip-events} (NEW):
- shard-kbl: NOTRUN -> [FAIL][2] +2 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-kbl7/igt@kms_async_flips@async-flip-with-page-flip-events.html
- shard-glk: NOTRUN -> [FAIL][3] +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-glk6/igt@kms_async_flips@async-flip-with-page-flip-events.html
* {igt@kms_async_flips@test-time-stamp} (NEW):
- shard-skl: NOTRUN -> [FAIL][4] +2 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-skl5/igt@kms_async_flips@test-time-stamp.html
New tests
---------
New tests have been introduced between CI_DRM_8965_full and Patchwork_18443_full:
### New IGT tests (4) ###
* igt@kms_async_flips@alternate-sync-async-flip:
- Statuses : 5 fail(s) 1 pass(s) 1 skip(s)
- Exec time: [0.0, 3.02] s
* igt@kms_async_flips@async-flip-with-page-flip-events:
- Statuses : 4 fail(s) 2 pass(s) 1 skip(s)
- Exec time: [0.0, 3.0] s
* igt@kms_async_flips@invalid-async-flip:
- Statuses : 5 pass(s) 1 skip(s)
- Exec time: [0.0, 0.04] s
* igt@kms_async_flips@test-time-stamp:
- Statuses : 4 fail(s) 2 pass(s) 1 skip(s)
- Exec time: [0.0, 0.36] s
Known issues
------------
Here are the changes found in Patchwork_18443_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_reloc@basic-many-active@vcs0:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#2389])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-glk7/igt@gem_exec_reloc@basic-many-active@vcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-glk4/igt@gem_exec_reloc@basic-many-active@vcs0.html
* igt@gem_exec_whisper@basic-normal-all:
- shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-glk2/igt@gem_exec_whisper@basic-normal-all.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-glk5/igt@gem_exec_whisper@basic-normal-all.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-random:
- shard-apl: [PASS][9] -> [FAIL][10] ([i915#1635] / [i915#54])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-64x64-random.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-apl6/igt@kms_cursor_crc@pipe-a-cursor-64x64-random.html
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#54])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-glk2/igt@kms_cursor_crc@pipe-a-cursor-64x64-random.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-glk2/igt@kms_cursor_crc@pipe-a-cursor-64x64-random.html
- shard-kbl: [PASS][13] -> [FAIL][14] ([i915#54])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-64x64-random.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-64x64-random.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#300])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-128x128-random:
- shard-skl: [PASS][17] -> [SKIP][18] ([fdo#109271]) +4 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-128x128-random.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-128x128-random.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-glk: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [PASS][23] -> [FAIL][24] ([i915#79])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@a-dp1:
- shard-apl: [PASS][25] -> [FAIL][26] ([i915#1635] / [i915#79])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-apl4/igt@kms_flip@flip-vs-expired-vblank@a-dp1.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-apl2/igt@kms_flip@flip-vs-expired-vblank@a-dp1.html
* igt@kms_flip@flip-vs-panning-interruptible@a-edp1:
- shard-skl: [PASS][27] -> [DMESG-WARN][28] ([i915#1982]) +48 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-skl10/igt@kms_flip@flip-vs-panning-interruptible@a-edp1.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-skl4/igt@kms_flip@flip-vs-panning-interruptible@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate@c-dp1:
- shard-kbl: [PASS][29] -> [FAIL][30] ([i915#2122])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-kbl7/igt@kms_flip@plain-flip-fb-recreate@c-dp1.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-kbl7/igt@kms_flip@plain-flip-fb-recreate@c-dp1.html
* igt@kms_frontbuffer_tracking@fbc-tiling-linear:
- shard-kbl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
- shard-tglb: [PASS][33] -> [DMESG-WARN][34] ([i915#1982]) +3 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][35] -> [FAIL][36] ([i915#1188]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-skl7/igt@kms_hdr@bpc-switch-dpms.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-skl: [PASS][37] -> [INCOMPLETE][38] ([i915#198])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-skl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-kbl: [PASS][39] -> [INCOMPLETE][40] ([CI#80] / [i915#155])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][41] -> [FAIL][42] ([fdo#108145] / [i915#265]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_dpms:
- shard-iclb: [PASS][43] -> [SKIP][44] ([fdo#109441]) +2 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-iclb2/igt@kms_psr@psr2_dpms.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-iclb8/igt@kms_psr@psr2_dpms.html
* igt@kms_vblank@pipe-b-ts-continuation-idle-hang:
- shard-apl: [PASS][45] -> [DMESG-WARN][46] ([i915#1635] / [i915#1982])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-apl6/igt@kms_vblank@pipe-b-ts-continuation-idle-hang.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-apl8/igt@kms_vblank@pipe-b-ts-continuation-idle-hang.html
* igt@perf@polling-parameterized:
- shard-iclb: [PASS][47] -> [FAIL][48] ([i915#1542])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-iclb1/igt@perf@polling-parameterized.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-iclb8/igt@perf@polling-parameterized.html
#### Possible fixes ####
* igt@gem_caching@writes:
- shard-skl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +42 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-skl3/igt@gem_caching@writes.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-skl2/igt@gem_caching@writes.html
* igt@gem_exec_reloc@basic-many-active@vecs0:
- shard-glk: [FAIL][51] ([i915#2389]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-glk7/igt@gem_exec_reloc@basic-many-active@vecs0.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-glk4/igt@gem_exec_reloc@basic-many-active@vecs0.html
* igt@gem_partial_pwrite_pread@reads-uncached:
- shard-glk: [FAIL][53] ([i915#2261]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-glk7/igt@gem_partial_pwrite_pread@reads-uncached.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-glk5/igt@gem_partial_pwrite_pread@reads-uncached.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [DMESG-WARN][55] ([i915#1436] / [i915#716]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-skl3/igt@gen9_exec_parse@allowed-single.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-skl4/igt@gen9_exec_parse@allowed-single.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-kbl: [INCOMPLETE][57] ([i915#1373] / [i915#726]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-kbl4/igt@i915_module_load@reload-with-fault-injection.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-kbl1/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_dc@dc5-psr:
- shard-iclb: [FAIL][59] ([i915#1899]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-iclb8/igt@i915_pm_dc@dc5-psr.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-iclb1/igt@i915_pm_dc@dc5-psr.html
* igt@i915_selftest@mock@requests:
- shard-skl: [INCOMPLETE][61] ([i915#198] / [i915#2278]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-skl9/igt@i915_selftest@mock@requests.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-skl9/igt@i915_selftest@mock@requests.html
* igt@kms_big_fb@linear-32bpp-rotate-180:
- shard-skl: [SKIP][63] ([fdo#109271]) -> [PASS][64] +12 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-skl7/igt@kms_big_fb@linear-32bpp-rotate-180.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-skl1/igt@kms_big_fb@linear-32bpp-rotate-180.html
* igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions:
- shard-kbl: [DMESG-WARN][65] ([i915#1982]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-kbl1/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-kbl1/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [INCOMPLETE][67] ([i915#155]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][69] ([i915#2122]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-glk8/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-glk9/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][71] ([i915#180]) -> [PASS][72] +5 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack:
- shard-iclb: [DMESG-WARN][73] ([i915#1982]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack.html
* igt@kms_frontbuffer_tracking@fbc-2p-shrfb-fliptrack:
- shard-glk: [FAIL][75] ([i915#49]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-glk5/igt@kms_frontbuffer_tracking@fbc-2p-shrfb-fliptrack.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-glk7/igt@kms_frontbuffer_tracking@fbc-2p-shrfb-fliptrack.html
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-tglb: [DMESG-WARN][77] ([i915#1982]) -> [PASS][78] +3 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-stridechange.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-stridechange.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][79] ([fdo#108145] / [i915#265]) -> [PASS][80] +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][81] ([fdo#109642] / [fdo#111068]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-iclb7/igt@kms_psr2_su@frontbuffer.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][83] ([fdo#109441]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-iclb1/igt@kms_psr@psr2_sprite_plane_move.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@perf@global-sseu-config:
- shard-iclb: [SKIP][85] ([i915#405]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-iclb5/igt@perf@global-sseu-config.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-iclb5/igt@perf@global-sseu-config.html
- shard-apl: [SKIP][87] ([fdo#109271] / [i915#1635]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-apl1/igt@perf@global-sseu-config.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-apl6/igt@perf@global-sseu-config.html
- shard-tglb: [SKIP][89] ([i915#405]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-tglb8/igt@perf@global-sseu-config.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-tglb7/igt@perf@global-sseu-config.html
- shard-glk: [SKIP][91] ([fdo#109271]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-glk9/igt@perf@global-sseu-config.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-glk5/igt@perf@global-sseu-config.html
- shard-kbl: [SKIP][93] ([fdo#109271]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-kbl1/igt@perf@global-sseu-config.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-kbl1/igt@perf@global-sseu-config.html
#### Warnings ####
* igt@i915_pm_dc@dc5-psr:
- shard-tglb: [FAIL][95] ([i915#1899]) -> [DMESG-WARN][96] ([i915#2411])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-tglb5/igt@i915_pm_dc@dc5-psr.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-tglb2/igt@i915_pm_dc@dc5-psr.html
* igt@kms_content_protection@srm:
- shard-apl: [TIMEOUT][97] ([i915#1319] / [i915#1635] / [i915#1958]) -> [TIMEOUT][98] ([i915#1319] / [i915#1635])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-apl4/igt@kms_content_protection@srm.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-apl2/igt@kms_content_protection@srm.html
* igt@kms_flip@flip-vs-suspend@a-edp1:
- shard-skl: [INCOMPLETE][99] ([i915#198]) -> [DMESG-WARN][100] ([i915#1982])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-skl2/igt@kms_flip@flip-vs-suspend@a-edp1.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-skl6/igt@kms_flip@flip-vs-suspend@a-edp1.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [SKIP][101] ([fdo#109271]) -> [FAIL][102] ([i915#1188])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-skl7/igt@kms_hdr@bpc-switch.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-skl7/igt@kms_hdr@bpc-switch.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-skl: [DMESG-FAIL][103] ([fdo#108145] / [i915#1982]) -> [FAIL][104] ([fdo#108145] / [i915#265])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@runner@aborted:
- shard-skl: ([FAIL][105], [FAIL][106]) ([i915#1436]) -> [FAIL][107] ([i915#2029])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-skl9/igt@runner@aborted.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8965/shard-skl3/igt@runner@aborted.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/shard-skl3/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1373]: https://gitlab.freedesktop.org/drm/intel/issues/1373
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899
[i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2261]: https://gitlab.freedesktop.org/drm/intel/issues/2261
[i915#2278]: https://gitlab.freedesktop.org/drm/intel/issues/2278
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300
[i915#405]: https://gitlab.freedesktop.org/drm/intel/issues/405
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#726]: https://gitlab.freedesktop.org/drm/intel/issues/726
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* IGT: IGT_5778 -> IGTPW_4951
* Linux: CI_DRM_8965 -> Patchwork_18443
CI-20190529: 20190529
CI_DRM_8965: f4cbf17fababf80c1c67c6f1687fb8bf7e00a263 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_4951: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4951/index.html
IGT_5778: 9a9db93fd2f2f59eb37b79d4b9a623067a945bac @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18443: 521ae51c4363f49a4a1a4cc47614f0bd2f8c8ca2 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18443/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2020-09-05 0:10 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-09-04 11:33 [PATCH v7 0/7] Asynchronous flip implementation for i915 Karthik B S
2020-09-04 11:33 ` [Intel-gfx] " Karthik B S
2020-09-04 11:33 ` [PATCH v7 1/7] drm/i915: Add enable/disable flip done and flip done handler Karthik B S
2020-09-04 11:33 ` [Intel-gfx] " Karthik B S
2020-09-04 11:33 ` [PATCH v7 2/7] drm/i915: Add support for async flips in I915 Karthik B S
2020-09-04 11:33 ` [Intel-gfx] " Karthik B S
2020-09-04 11:33 ` [PATCH v7 3/7] drm/i915: Add checks specific to async flips Karthik B S
2020-09-04 11:33 ` [Intel-gfx] " Karthik B S
2020-09-04 11:33 ` [PATCH v7 4/7] drm/i915: Do not call drm_crtc_arm_vblank_event in " Karthik B S
2020-09-04 11:33 ` [Intel-gfx] " Karthik B S
2020-09-04 11:33 ` [PATCH v7 5/7] drm/i915: Add dedicated plane hook for async flip case Karthik B S
2020-09-04 11:33 ` [Intel-gfx] " Karthik B S
2020-09-04 11:33 ` [PATCH v7 6/7] Documentation/gpu: Add asynchronous flip documentation for i915 Karthik B S
2020-09-04 11:33 ` [Intel-gfx] " Karthik B S
2020-09-04 11:33 ` [PATCH v7 7/7] drm/i915: Enable async flips in i915 Karthik B S
2020-09-04 11:33 ` [Intel-gfx] " Karthik B S
2020-09-04 13:45 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Asynchronous flip implementation for i915 (rev7) Patchwork
2020-09-04 14:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-09-05 0:10 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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