* [PATCH 1/6] drm/amd: Mark some tables as const
@ 2016-04-10 14:29 Nils Wallménius
2016-04-10 14:30 ` [PATCH 2/6] drm/amd/scheduler: Mark amdgpu_sched_ops const Nils Wallménius
` (5 more replies)
0 siblings, 6 replies; 8+ messages in thread
From: Nils Wallménius @ 2016-04-10 14:29 UTC (permalink / raw
To: dri-devel; +Cc: Nils Wallménius
This patch marks some compile-time constant tables 'const'.
The tables marked in this patch are the low hanging fruit
where little other changes were necesary to avoid casting
away constness etc. Also mark some tables that are private
to a file as static.
Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 12 ++++++------
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h | 2 +-
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c | 10 +++++-----
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 8 ++++----
drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h | 2 +-
drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c | 2 +-
drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 6 +++---
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 2 +-
13 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 66e51f9..5d05b5d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -2348,7 +2348,7 @@ static inline void amdgpu_unregister_atpx_handler(void) {}
* KMS
*/
extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
-extern int amdgpu_max_kms_ioctl;
+extern const int amdgpu_max_kms_ioctl;
int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
int amdgpu_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 0535095..c835abe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -596,20 +596,20 @@ const struct drm_mode_config_funcs amdgpu_mode_funcs = {
.output_poll_changed = amdgpu_output_poll_changed
};
-static struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
+static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
{ { UNDERSCAN_OFF, "off" },
{ UNDERSCAN_ON, "on" },
{ UNDERSCAN_AUTO, "auto" },
};
-static struct drm_prop_enum_list amdgpu_audio_enum_list[] =
+static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
{ { AMDGPU_AUDIO_DISABLE, "off" },
{ AMDGPU_AUDIO_ENABLE, "on" },
{ AMDGPU_AUDIO_AUTO, "auto" },
};
/* XXX support different dither options? spatial, temporal, both, etc. */
-static struct drm_prop_enum_list amdgpu_dither_enum_list[] =
+static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
{ { AMDGPU_FMT_DITHER_DISABLE, "off" },
{ AMDGPU_FMT_DITHER_ENABLE, "on" },
};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index f1e17d6..2d9dbc2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -166,7 +166,7 @@ module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
-static struct pci_device_id pciidlist[] = {
+static const struct pci_device_id pciidlist[] = {
#ifdef CONFIG_DRM_AMDGPU_CIK
/* Kaveri */
{0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 762cfdb..9266c7b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -498,7 +498,7 @@ static int amdgpu_irqdomain_map(struct irq_domain *d,
return 0;
}
-static struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
+static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
.map = amdgpu_irqdomain_map,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 7805a87..1f9d318 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -754,4 +754,4 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
};
-int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
+const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
index 025a3ed..55a006d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
@@ -95,23 +95,23 @@ enum DPM_EVENT_SRC {
/* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
* not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
*/
-uint16_t fiji_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0},
- {600, 1050, 6, 1} };
+static const uint16_t fiji_clock_stretcher_lookup_table[2][4] =
+{ {600, 1050, 3, 0}, {600, 1050, 6, 1} };
/* [FF, SS] type, [] 4 voltage ranges, and
* [Floor Freq, Boundary Freq, VID min , VID max]
*/
-uint32_t fiji_clock_stretcher_ddt_table[2][4][4] =
+static const uint32_t fiji_clock_stretcher_ddt_table[2][4][4] =
{ { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
{ {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
* (coming from PWR_CKS_CNTL.stretch_amount reg spec)
*/
-uint8_t fiji_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5},
- {0, 2, 4, 5, 6, 5} };
+static const uint8_t fiji_clock_stretch_amount_conversion[2][6] =
+{ {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
-const unsigned long PhwFiji_Magic = (unsigned long)(PHM_VIslands_Magic);
+static const unsigned long PhwFiji_Magic = (unsigned long)(PHM_VIslands_Magic);
struct fiji_power_state *cast_phw_fiji_power_state(
struct pp_hw_power_state *hw_ps)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
index a16f7cd..4b29d9e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
@@ -263,7 +263,7 @@ struct fiji_hwmgr {
bool enable_tdc_limit_feature;
bool enable_pkg_pwr_tracking_feature;
bool disable_uvd_power_tune_feature;
- struct fiji_pt_defaults *power_tune_defaults;
+ const struct fiji_pt_defaults *power_tune_defaults;
struct SMU73_Discrete_PmFuses power_tune_table;
uint32_t dte_tj_offset;
uint32_t fast_watermark_threshold;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
index 6efcb2b..db23a40 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
@@ -32,7 +32,7 @@
#define VOLTAGE_SCALE 4
#define POWERTUNE_DEFAULT_SET_MAX 1
-struct fiji_pt_defaults fiji_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
+const struct fiji_pt_defaults fiji_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
/*sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc */
{1, 0xF, 0xFD,
/* TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase */
@@ -143,7 +143,7 @@ static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t* sda)
int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
{
struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
- struct fiji_pt_defaults *defaults = data->power_tune_defaults;
+ const struct fiji_pt_defaults *defaults = data->power_tune_defaults;
SMU73_Discrete_DpmTable *dpm_table = &(data->smc_state_table);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
@@ -222,7 +222,7 @@ int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
static int fiji_populate_svi_load_line(struct pp_hwmgr *hwmgr)
{
struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
- struct fiji_pt_defaults *defaults = data->power_tune_defaults;
+ const struct fiji_pt_defaults *defaults = data->power_tune_defaults;
data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
@@ -238,7 +238,7 @@ static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr)
struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct fiji_pt_defaults *defaults = data->power_tune_defaults;
+ const struct fiji_pt_defaults *defaults = data->power_tune_defaults;
/* TDC number of fraction bits are changed from 8 to 7
* for Fiji as requested by SMC team
@@ -256,7 +256,7 @@ static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr)
static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
{
struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
- struct fiji_pt_defaults *defaults = data->power_tune_defaults;
+ const struct fiji_pt_defaults *defaults = data->power_tune_defaults;
uint32_t temp;
if (fiji_read_smc_sram_dword(hwmgr->smumgr,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
index fee7835..2e99a14 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
@@ -86,17 +86,17 @@
typedef uint32_t PECI_RegistryValue;
/* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */
-uint16_t PP_ClockStretcherLookupTable[2][4] = {
+static const uint16_t PP_ClockStretcherLookupTable[2][4] = {
{600, 1050, 3, 0},
{600, 1050, 6, 1} };
/* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
-uint32_t PP_ClockStretcherDDTTable[2][4][4] = {
+static const uint32_t PP_ClockStretcherDDTTable[2][4][4] = {
{ {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
{ {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
-uint8_t PP_ClockStretchAmountConversion[2][6] = {
+static const uint8_t PP_ClockStretchAmountConversion[2][6] = {
{0, 1, 3, 2, 4, 5},
{0, 2, 4, 5, 6, 5} };
@@ -110,7 +110,7 @@ enum DPM_EVENT_SRC {
};
typedef enum DPM_EVENT_SRC DPM_EVENT_SRC;
-const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic);
+static const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic);
struct tonga_power_state *cast_phw_tonga_power_state(
struct pp_hw_power_state *hw_ps)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
index 0262ad3..8a31665 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
@@ -46,7 +46,7 @@ struct PWR_Command_Table
typedef struct PWR_Command_Table PWR_Command_Table;
#define PWR_VIRUS_TABLE_SIZE 10243
-static PWR_Command_Table PwrVirusTable[PWR_VIRUS_TABLE_SIZE] =
+static const PWR_Command_Table PwrVirusTable[PWR_VIRUS_TABLE_SIZE] =
{
{ PwrCmdWrite, 0x100100b6, mmPCIE_INDEX },
{ PwrCmdWrite, 0x00000000, mmPCIE_DATA },
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
index ec222c6..da18f44 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
@@ -39,7 +39,7 @@
#define SIZE_ALIGN_32(x) (((x) + 31) / 32 * 32)
-static enum cz_scratch_entry firmware_list[] = {
+static const enum cz_scratch_entry firmware_list[] = {
CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0,
CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index cdbb9f8..673a75c 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -44,7 +44,7 @@
#define FIJI_SMC_SIZE 0x20000
-struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] = {
+static const struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] = {
/* Min Sclk pcie DeepSleep Activity CgSpll CgSpll spllSpread SpllSpread CcPwr CcPwr Sclk Display Enabled Enabled Voltage Power */
/* Voltage, Frequency, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, Spectrum, Spectrum2, DynRm, DynRm1 Did, Watermark, ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
{ 0x3c0fd047, 0x30750000, 0x00, 0x03, 0x1e00, 0x00200410, 0x87020000, 0x21680000, 0x0c000000, 0, 0, 0x16, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 },
@@ -189,7 +189,7 @@ int fiji_copy_bytes_to_smc(struct pp_smumgr *smumgr,
int fiji_program_jump_on_start(struct pp_smumgr *smumgr)
{
- static unsigned char data[] = { 0xE0, 0x00, 0x80, 0x40 };
+ static const unsigned char data[] = { 0xE0, 0x00, 0x80, 0x40 };
fiji_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data) + 1);
@@ -665,7 +665,7 @@ int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
{
int i, result = -1;
uint32_t reg, data;
- PWR_Command_Table *virus = PwrVirusTable;
+ const PWR_Command_Table *virus = PwrVirusTable;
struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
priv->avfs.AvfsBtcStatus = AVFS_LOAD_VIRUS;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index ebdb43a..32820b6 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -145,7 +145,7 @@ out:
int tonga_program_jump_on_start(struct pp_smumgr *smumgr)
{
- static unsigned char pData[] = { 0xE0, 0x00, 0x80, 0x40 };
+ static const unsigned char pData[] = { 0xE0, 0x00, 0x80, 0x40 };
tonga_copy_bytes_to_smc(smumgr, 0x0, pData, 4, sizeof(pData)+1);
--
2.8.0.rc3
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/6] drm/amd/scheduler: Mark amdgpu_sched_ops const
2016-04-10 14:29 [PATCH 1/6] drm/amd: Mark some tables as const Nils Wallménius
@ 2016-04-10 14:30 ` Nils Wallménius
2016-04-10 14:30 ` [PATCH 3/6] drm/amdgpu: Mark all instances of struct drm_info_list as const Nils Wallménius
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Nils Wallménius @ 2016-04-10 14:30 UTC (permalink / raw
To: dri-devel; +Cc: Nils Wallménius
This marks the struct amdgpu_sched_ops const and
adjusts amd_sched_init to take a const pointer
for the ops param. The ops member of
struct amd_gpu_scheduler is also changed to const.
Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 +-
drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 2 +-
drivers/gpu/drm/amd/scheduler/gpu_scheduler.h | 4 ++--
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 5d05b5d..660213a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -748,7 +748,7 @@ enum amdgpu_ring_type {
AMDGPU_RING_TYPE_VCE
};
-extern struct amd_sched_backend_ops amdgpu_sched_ops;
+extern const struct amd_sched_backend_ops amdgpu_sched_ops;
int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
struct amdgpu_job **job);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index a052ac2..4eea2a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -198,7 +198,7 @@ err:
return fence;
}
-struct amd_sched_backend_ops amdgpu_sched_ops = {
+const struct amd_sched_backend_ops amdgpu_sched_ops = {
.dependency = amdgpu_job_dependency,
.run_job = amdgpu_job_run,
.begin_job = amd_sched_job_begin,
diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
index 639c70d..c16248c 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
@@ -530,7 +530,7 @@ static int amd_sched_main(void *param)
* Return 0 on success, otherwise error code.
*/
int amd_sched_init(struct amd_gpu_scheduler *sched,
- struct amd_sched_backend_ops *ops,
+ const struct amd_sched_backend_ops *ops,
unsigned hw_submission, long timeout, const char *name)
{
int i;
diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
index 95ebfd0..169f70f 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
@@ -123,7 +123,7 @@ enum amd_sched_priority {
* One scheduler is implemented for each hardware ring
*/
struct amd_gpu_scheduler {
- struct amd_sched_backend_ops *ops;
+ const struct amd_sched_backend_ops *ops;
uint32_t hw_submission_limit;
long timeout;
const char *name;
@@ -137,7 +137,7 @@ struct amd_gpu_scheduler {
};
int amd_sched_init(struct amd_gpu_scheduler *sched,
- struct amd_sched_backend_ops *ops,
+ const struct amd_sched_backend_ops *ops,
uint32_t hw_submission, long timeout, const char *name);
void amd_sched_fini(struct amd_gpu_scheduler *sched);
--
2.8.0.rc3
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/6] drm/amdgpu: Mark all instances of struct drm_info_list as const
2016-04-10 14:29 [PATCH 1/6] drm/amd: Mark some tables as const Nils Wallménius
2016-04-10 14:30 ` [PATCH 2/6] drm/amd/scheduler: Mark amdgpu_sched_ops const Nils Wallménius
@ 2016-04-10 14:30 ` Nils Wallménius
2016-04-10 14:30 ` [PATCH 4/6] drm/amd/powerplay: Mark pem_event_action chains " Nils Wallménius
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Nils Wallménius @ 2016-04-10 14:30 UTC (permalink / raw
To: dri-devel; +Cc: Nils Wallménius
All these are compile time constand and the
drm_debugfs_create/remove_files functions take a const
pointer argument.
Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
8 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 660213a..d1ad763 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1701,12 +1701,12 @@ static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
* Debugfs
*/
struct amdgpu_debugfs {
- struct drm_info_list *files;
+ const struct drm_info_list *files;
unsigned num_files;
};
int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
- struct drm_info_list *files,
+ const struct drm_info_list *files,
unsigned nfiles);
int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 00fa730..e3905c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2022,7 +2022,7 @@ void amdgpu_get_pcie_info(struct amdgpu_device *adev)
* Debugfs
*/
int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
- struct drm_info_list *files,
+ const struct drm_info_list *files,
unsigned nfiles)
{
unsigned i;
@@ -2193,7 +2193,7 @@ static int amdgpu_debugfs_print_status(struct seq_file *m, void *data)
return 0;
}
-static struct drm_info_list amdgpu_debugfs_status_list[] = {
+static const struct drm_info_list amdgpu_debugfs_status_list[] = {
{"amdgpu_print_status", &amdgpu_debugfs_print_status, 0, NULL},
};
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index d81f1f4..100f4c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -639,7 +639,7 @@ static int amdgpu_debugfs_gpu_reset(struct seq_file *m, void *data)
return 0;
}
-static struct drm_info_list amdgpu_debugfs_fence_list[] = {
+static const struct drm_info_list amdgpu_debugfs_fence_list[] = {
{"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
{"amdgpu_gpu_reset", &amdgpu_debugfs_gpu_reset, 0, NULL}
};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index fa6a27b..0635bb6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -797,7 +797,7 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
return 0;
}
-static struct drm_info_list amdgpu_debugfs_gem_list[] = {
+static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
{"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
};
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 83973d0..0129617 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -329,7 +329,7 @@ static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data)
}
-static struct drm_info_list amdgpu_debugfs_sa_list[] = {
+static const struct drm_info_list amdgpu_debugfs_sa_list[] = {
{"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL},
};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index ff9597c..6d44d4a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1212,7 +1212,7 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
return 0;
}
-static struct drm_info_list amdgpu_pm_info_list[] = {
+static const struct drm_info_list amdgpu_pm_info_list[] = {
{"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
};
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index dd79243..7bd31ae 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -427,7 +427,7 @@ static int r600_uvd_index = offsetof(struct amdgpu_device, uvd.ring);
static int si_vce1_index = offsetof(struct amdgpu_device, vce.ring[0]);
static int si_vce2_index = offsetof(struct amdgpu_device, vce.ring[1]);
-static struct drm_info_list amdgpu_debugfs_ring_info_list[] = {
+static const struct drm_info_list amdgpu_debugfs_ring_info_list[] = {
{"amdgpu_ring_gfx", amdgpu_debugfs_ring_info, 0, &amdgpu_gfx_index},
{"amdgpu_ring_cp1", amdgpu_debugfs_ring_info, 0, &cayman_cp1_index},
{"amdgpu_ring_cp2", amdgpu_debugfs_ring_info, 0, &cayman_cp2_index},
@@ -445,7 +445,7 @@ static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, struct amdgpu_ri
#if defined(CONFIG_DEBUG_FS)
unsigned i;
for (i = 0; i < ARRAY_SIZE(amdgpu_debugfs_ring_info_list); ++i) {
- struct drm_info_list *info = &amdgpu_debugfs_ring_info_list[i];
+ const struct drm_info_list *info = &amdgpu_debugfs_ring_info_list[i];
int roffset = *(int*)amdgpu_debugfs_ring_info_list[i].data;
struct amdgpu_ring *other = (void *)(((uint8_t*)adev) + roffset);
unsigned r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index c9692ad..43e8954 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1165,7 +1165,7 @@ static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
static int ttm_pl_vram = TTM_PL_VRAM;
static int ttm_pl_tt = TTM_PL_TT;
-static struct drm_info_list amdgpu_ttm_debugfs_list[] = {
+static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
{"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
{"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
{"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
--
2.8.0.rc3
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 4/6] drm/amd/powerplay: Mark pem_event_action chains as const
2016-04-10 14:29 [PATCH 1/6] drm/amd: Mark some tables as const Nils Wallménius
2016-04-10 14:30 ` [PATCH 2/6] drm/amd/scheduler: Mark amdgpu_sched_ops const Nils Wallménius
2016-04-10 14:30 ` [PATCH 3/6] drm/amdgpu: Mark all instances of struct drm_info_list as const Nils Wallménius
@ 2016-04-10 14:30 ` Nils Wallménius
2016-04-10 14:30 ` [PATCH 5/6] drm/amd/powerplay: mark phm_master_table_* structs " Nils Wallménius
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Nils Wallménius @ 2016-04-10 14:30 UTC (permalink / raw
To: dri-devel; +Cc: Nils Wallménius
As these arrays were of pointer to pointer type, they were
pointer to pointer to const. Make them pointer to const
pointer to const.
Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
---
.../drm/amd/powerplay/eventmgr/eventactionchains.c | 34 +++++++++++-----------
.../drm/amd/powerplay/eventmgr/eventmanagement.c | 2 +-
drivers/gpu/drm/amd/powerplay/inc/eventmgr.h | 2 +-
3 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
index 56856a2..d6635cc 100644
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
@@ -24,7 +24,7 @@
#include "eventactionchains.h"
#include "eventsubchains.h"
-static const pem_event_action *initialize_event[] = {
+static const pem_event_action * const initialize_event[] = {
block_adjust_power_state_tasks,
power_budget_tasks,
system_config_tasks,
@@ -45,7 +45,7 @@ const struct action_chain initialize_action_chain = {
initialize_event
};
-static const pem_event_action *uninitialize_event[] = {
+static const pem_event_action * const uninitialize_event[] = {
ungate_all_display_phys_tasks,
uninitialize_display_phy_access_tasks,
disable_gfx_voltage_island_power_gating_tasks,
@@ -64,7 +64,7 @@ const struct action_chain uninitialize_action_chain = {
uninitialize_event
};
-static const pem_event_action *power_source_change_event_pp_enabled[] = {
+static const pem_event_action * const power_source_change_event_pp_enabled[] = {
set_power_source_tasks,
set_power_saving_state_tasks,
adjust_power_state_tasks,
@@ -79,7 +79,7 @@ const struct action_chain power_source_change_action_chain_pp_enabled = {
power_source_change_event_pp_enabled
};
-static const pem_event_action *power_source_change_event_pp_disabled[] = {
+static const pem_event_action * const power_source_change_event_pp_disabled[] = {
set_power_source_tasks,
set_nbmcu_state_tasks,
NULL
@@ -90,7 +90,7 @@ const struct action_chain power_source_changes_action_chain_pp_disabled = {
power_source_change_event_pp_disabled
};
-static const pem_event_action *power_source_change_event_hardware_dc[] = {
+static const pem_event_action * const power_source_change_event_hardware_dc[] = {
set_power_source_tasks,
set_power_saving_state_tasks,
adjust_power_state_tasks,
@@ -106,7 +106,7 @@ const struct action_chain power_source_change_action_chain_hardware_dc = {
power_source_change_event_hardware_dc
};
-static const pem_event_action *suspend_event[] = {
+static const pem_event_action * const suspend_event[] = {
reset_display_phy_access_tasks,
unregister_interrupt_tasks,
disable_gfx_voltage_island_power_gating_tasks,
@@ -130,7 +130,7 @@ const struct action_chain suspend_action_chain = {
suspend_event
};
-static const pem_event_action *resume_event[] = {
+static const pem_event_action * const resume_event[] = {
unblock_hw_access_tasks,
resume_connected_standby_tasks,
notify_smu_resume_tasks,
@@ -164,7 +164,7 @@ const struct action_chain resume_action_chain = {
resume_event
};
-static const pem_event_action *complete_init_event[] = {
+static const pem_event_action * const complete_init_event[] = {
unblock_adjust_power_state_tasks,
adjust_power_state_tasks,
enable_gfx_clock_gating_tasks,
@@ -178,7 +178,7 @@ const struct action_chain complete_init_action_chain = {
complete_init_event
};
-static const pem_event_action *enable_gfx_clock_gating_event[] = {
+static const pem_event_action * const enable_gfx_clock_gating_event[] = {
enable_gfx_clock_gating_tasks,
NULL
};
@@ -188,7 +188,7 @@ const struct action_chain enable_gfx_clock_gating_action_chain = {
enable_gfx_clock_gating_event
};
-static const pem_event_action *disable_gfx_clock_gating_event[] = {
+static const pem_event_action * const disable_gfx_clock_gating_event[] = {
disable_gfx_clock_gating_tasks,
NULL
};
@@ -198,7 +198,7 @@ const struct action_chain disable_gfx_clock_gating_action_chain = {
disable_gfx_clock_gating_event
};
-static const pem_event_action *enable_cgpg_event[] = {
+static const pem_event_action * const enable_cgpg_event[] = {
enable_cgpg_tasks,
NULL
};
@@ -208,7 +208,7 @@ const struct action_chain enable_cgpg_action_chain = {
enable_cgpg_event
};
-static const pem_event_action *disable_cgpg_event[] = {
+static const pem_event_action * const disable_cgpg_event[] = {
disable_cgpg_tasks,
NULL
};
@@ -221,7 +221,7 @@ const struct action_chain disable_cgpg_action_chain = {
/* Enable user _2d performance and activate */
-static const pem_event_action *enable_user_state_event[] = {
+static const pem_event_action * const enable_user_state_event[] = {
create_new_user_performance_state_tasks,
adjust_power_state_tasks,
NULL
@@ -232,7 +232,7 @@ const struct action_chain enable_user_state_action_chain = {
enable_user_state_event
};
-static const pem_event_action *enable_user_2d_performance_event[] = {
+static const pem_event_action * const enable_user_2d_performance_event[] = {
enable_user_2d_performance_tasks,
add_user_2d_performance_state_tasks,
set_performance_state_tasks,
@@ -247,7 +247,7 @@ const struct action_chain enable_user_2d_performance_action_chain = {
};
-static const pem_event_action *disable_user_2d_performance_event[] = {
+static const pem_event_action * const disable_user_2d_performance_event[] = {
disable_user_2d_performance_tasks,
delete_user_2d_performance_state_tasks,
NULL
@@ -259,7 +259,7 @@ const struct action_chain disable_user_2d_performance_action_chain = {
};
-static const pem_event_action *display_config_change_event[] = {
+static const pem_event_action * const display_config_change_event[] = {
/* countDisplayConfigurationChangeEventTasks, */
unblock_adjust_power_state_tasks,
set_cpu_power_state,
@@ -278,7 +278,7 @@ const struct action_chain display_config_change_action_chain = {
display_config_change_event
};
-static const pem_event_action *readjust_power_state_event[] = {
+static const pem_event_action * const readjust_power_state_event[] = {
adjust_power_state_tasks,
NULL
};
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.c
index 1e2ad56..cd1ca07 100644
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.c
+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.c
@@ -62,7 +62,7 @@ int pem_init_event_action_chains(struct pp_eventmgr *eventmgr)
int pem_excute_event_chain(struct pp_eventmgr *eventmgr, const struct action_chain *event_chain, struct pem_event_data *event_data)
{
- const pem_event_action **paction_chain;
+ const pem_event_action * const *paction_chain;
const pem_event_action *psub_chain;
int tmp_result = 0;
int result = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h b/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h
index 10437dc..d63ef83 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h
@@ -37,7 +37,7 @@ typedef int (*pem_event_action)(struct pp_eventmgr *eventmgr,
struct action_chain {
const char *description; /* action chain description for debugging purpose */
- const pem_event_action **action_chain; /* pointer to chain of event actions */
+ const pem_event_action * const *action_chain; /* pointer to chain of event actions */
};
struct pem_power_source_ui_state_info {
--
2.8.0.rc3
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 5/6] drm/amd/powerplay: mark phm_master_table_* structs as const
2016-04-10 14:29 [PATCH 1/6] drm/amd: Mark some tables as const Nils Wallménius
` (2 preceding siblings ...)
2016-04-10 14:30 ` [PATCH 4/6] drm/amd/powerplay: Mark pem_event_action chains " Nils Wallménius
@ 2016-04-10 14:30 ` Nils Wallménius
2016-04-10 14:30 ` [PATCH 6/6] drm/amd: make some function-local tables static const Nils Wallménius
2016-04-11 7:32 ` [PATCH 1/6] drm/amd: Mark some tables as const Christian König
5 siblings, 0 replies; 8+ messages in thread
From: Nils Wallménius @ 2016-04-10 14:30 UTC (permalink / raw
To: dri-devel; +Cc: Nils Wallménius
Also adjust phm_construct_table to take a const pointer
Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
---
.../drm/amd/powerplay/hwmgr/cz_clockpowergating.c | 4 ++--
.../drm/amd/powerplay/hwmgr/cz_clockpowergating.h | 2 +-
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 20 ++++++++++----------
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c | 8 ++++----
drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c | 2 +-
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c | 8 ++++----
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 4 ++--
7 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
index ff08ce4..436fc16 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
@@ -237,7 +237,7 @@ int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
}
-static struct phm_master_table_item cz_enable_clock_power_gatings_list[] = {
+static const struct phm_master_table_item cz_enable_clock_power_gatings_list[] = {
/*we don't need an exit table here, because there is only D3 cold on Kv*/
{ phm_cf_want_uvd_power_gating, cz_tf_uvd_power_gating_initialize },
{ phm_cf_want_vce_power_gating, cz_tf_vce_power_gating_initialize },
@@ -245,7 +245,7 @@ static struct phm_master_table_item cz_enable_clock_power_gatings_list[] = {
{ NULL, NULL }
};
-struct phm_master_table_header cz_phm_enable_clock_power_gatings_master = {
+const struct phm_master_table_header cz_phm_enable_clock_power_gatings_master = {
0,
PHM_MasterTableFlag_None,
cz_enable_clock_power_gatings_list
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h
index bbbc057..35e1b36 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h
@@ -28,7 +28,7 @@
#include "pp_asicblocks.h"
extern int cz_phm_set_asic_block_gating(struct pp_hwmgr *hwmgr, enum PHM_AsicBlock block, enum PHM_ClockGateSetting gating);
-extern struct phm_master_table_header cz_phm_enable_clock_power_gatings_master;
+extern const struct phm_master_table_header cz_phm_enable_clock_power_gatings_master;
extern struct phm_master_table_header cz_phm_disable_clock_power_gatings_master;
extern int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
extern int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index 5682490..648394f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -915,7 +915,7 @@ static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
return 0;
}
-static struct phm_master_table_item cz_set_power_state_list[] = {
+static const struct phm_master_table_item cz_set_power_state_list[] = {
{NULL, cz_tf_update_sclk_limit},
{NULL, cz_tf_set_deep_sleep_sclk_threshold},
{NULL, cz_tf_set_watermark_threshold},
@@ -925,13 +925,13 @@ static struct phm_master_table_item cz_set_power_state_list[] = {
{NULL, NULL}
};
-static struct phm_master_table_header cz_set_power_state_master = {
+static const struct phm_master_table_header cz_set_power_state_master = {
0,
PHM_MasterTableFlag_None,
cz_set_power_state_list
};
-static struct phm_master_table_item cz_setup_asic_list[] = {
+static const struct phm_master_table_item cz_setup_asic_list[] = {
{NULL, cz_tf_reset_active_process_mask},
{NULL, cz_tf_upload_pptable_to_smu},
{NULL, cz_tf_init_sclk_limit},
@@ -943,7 +943,7 @@ static struct phm_master_table_item cz_setup_asic_list[] = {
{NULL, NULL}
};
-static struct phm_master_table_header cz_setup_asic_master = {
+static const struct phm_master_table_header cz_setup_asic_master = {
0,
PHM_MasterTableFlag_None,
cz_setup_asic_list
@@ -984,14 +984,14 @@ static int cz_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
return 0;
}
-static struct phm_master_table_item cz_power_down_asic_list[] = {
+static const struct phm_master_table_item cz_power_down_asic_list[] = {
{NULL, cz_tf_power_up_display_clock_sys_pll},
{NULL, cz_tf_clear_nb_dpm_flag},
{NULL, cz_tf_reset_cc6_data},
{NULL, NULL}
};
-static struct phm_master_table_header cz_power_down_asic_master = {
+static const struct phm_master_table_header cz_power_down_asic_master = {
0,
PHM_MasterTableFlag_None,
cz_power_down_asic_list
@@ -1095,19 +1095,19 @@ static int cz_tf_check_for_dpm_enabled(struct pp_hwmgr *hwmgr,
return 0;
}
-static struct phm_master_table_item cz_disable_dpm_list[] = {
+static const struct phm_master_table_item cz_disable_dpm_list[] = {
{ NULL, cz_tf_check_for_dpm_enabled},
{NULL, NULL},
};
-static struct phm_master_table_header cz_disable_dpm_master = {
+static const struct phm_master_table_header cz_disable_dpm_master = {
0,
PHM_MasterTableFlag_None,
cz_disable_dpm_list
};
-static struct phm_master_table_item cz_enable_dpm_list[] = {
+static const struct phm_master_table_item cz_enable_dpm_list[] = {
{ NULL, cz_tf_check_for_dpm_disabled },
{ NULL, cz_tf_program_voting_clients },
{ NULL, cz_tf_start_dpm},
@@ -1117,7 +1117,7 @@ static struct phm_master_table_item cz_enable_dpm_list[] = {
{NULL, NULL},
};
-static struct phm_master_table_header cz_enable_dpm_master = {
+static const struct phm_master_table_header cz_enable_dpm_master = {
0,
PHM_MasterTableFlag_None,
cz_enable_dpm_list
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c
index e76a7de..e2b448f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c
@@ -615,7 +615,7 @@ static int tf_fiji_thermal_disable_alert(struct pp_hwmgr *hwmgr,
return fiji_thermal_disable_alert(hwmgr);
}
-static struct phm_master_table_item
+static const struct phm_master_table_item
fiji_thermal_start_thermal_controller_master_list[] = {
{NULL, tf_fiji_thermal_initialize},
{NULL, tf_fiji_thermal_set_temperature_range},
@@ -630,14 +630,14 @@ fiji_thermal_start_thermal_controller_master_list[] = {
{NULL, NULL}
};
-static struct phm_master_table_header
+static const struct phm_master_table_header
fiji_thermal_start_thermal_controller_master = {
0,
PHM_MasterTableFlag_None,
fiji_thermal_start_thermal_controller_master_list
};
-static struct phm_master_table_item
+static const struct phm_master_table_item
fiji_thermal_set_temperature_range_master_list[] = {
{NULL, tf_fiji_thermal_disable_alert},
{NULL, tf_fiji_thermal_set_temperature_range},
@@ -645,7 +645,7 @@ fiji_thermal_set_temperature_range_master_list[] = {
{NULL, NULL}
};
-struct phm_master_table_header
+static const struct phm_master_table_header
fiji_thermal_set_temperature_range_master = {
0,
PHM_MasterTableFlag_None,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
index 72cfecc..7a705ce 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
@@ -84,7 +84,7 @@ int phm_dispatch_table(struct pp_hwmgr *hwmgr,
}
int phm_construct_table(struct pp_hwmgr *hwmgr,
- struct phm_master_table_header *master_table,
+ const struct phm_master_table_header *master_table,
struct phm_runtime_table_header *rt_table)
{
uint32_t function_count = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
index a188174..23f8463 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
@@ -525,7 +525,7 @@ static int tf_tonga_thermal_disable_alert(struct pp_hwmgr *hwmgr, void *input, v
return tonga_thermal_disable_alert(hwmgr);
}
-static struct phm_master_table_item tonga_thermal_start_thermal_controller_master_list[] = {
+static const struct phm_master_table_item tonga_thermal_start_thermal_controller_master_list[] = {
{ NULL, tf_tonga_thermal_initialize },
{ NULL, tf_tonga_thermal_set_temperature_range },
{ NULL, tf_tonga_thermal_enable_alert },
@@ -538,20 +538,20 @@ static struct phm_master_table_item tonga_thermal_start_thermal_controller_maste
{ NULL, NULL }
};
-static struct phm_master_table_header tonga_thermal_start_thermal_controller_master = {
+static const struct phm_master_table_header tonga_thermal_start_thermal_controller_master = {
0,
PHM_MasterTableFlag_None,
tonga_thermal_start_thermal_controller_master_list
};
-static struct phm_master_table_item tonga_thermal_set_temperature_range_master_list[] = {
+static const struct phm_master_table_item tonga_thermal_set_temperature_range_master_list[] = {
{ NULL, tf_tonga_thermal_disable_alert},
{ NULL, tf_tonga_thermal_set_temperature_range},
{ NULL, tf_tonga_thermal_enable_alert},
{ NULL, NULL }
};
-struct phm_master_table_header tonga_thermal_set_temperature_range_master = {
+static const struct phm_master_table_header tonga_thermal_set_temperature_range_master = {
0,
PHM_MasterTableFlag_None,
tonga_thermal_set_temperature_range_master_list
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 928f5a7..e1ca36c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -141,7 +141,7 @@ enum phm_master_table_flag {
struct phm_master_table_header {
uint32_t storage_size;
uint32_t flags;
- struct phm_master_table_item *master_list;
+ const struct phm_master_table_item *master_list;
};
struct phm_runtime_table_header {
@@ -199,7 +199,7 @@ extern int phm_dispatch_table(struct pp_hwmgr *hwmgr,
void *input, void *output);
extern int phm_construct_table(struct pp_hwmgr *hwmgr,
- struct phm_master_table_header *master_table,
+ const struct phm_master_table_header *master_table,
struct phm_runtime_table_header *rt_table);
extern int phm_destroy_table(struct pp_hwmgr *hwmgr,
--
2.8.0.rc3
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 6/6] drm/amd: make some function-local tables static const
2016-04-10 14:29 [PATCH 1/6] drm/amd: Mark some tables as const Nils Wallménius
` (3 preceding siblings ...)
2016-04-10 14:30 ` [PATCH 5/6] drm/amd/powerplay: mark phm_master_table_* structs " Nils Wallménius
@ 2016-04-10 14:30 ` Nils Wallménius
2016-04-11 7:32 ` [PATCH 1/6] drm/amd: Mark some tables as const Christian König
5 siblings, 0 replies; 8+ messages in thread
From: Nils Wallménius @ 2016-04-10 14:30 UTC (permalink / raw
To: dri-devel; +Cc: Nils Wallménius
These tables were initialized on stack on each call, avoid that
and save a little bit of text size.
Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 2 +-
drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h | 8 ++++----
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
index cd639c3..33e47a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
@@ -141,7 +141,7 @@ out_cleanup:
void amdgpu_benchmark(struct amdgpu_device *adev, int test_number)
{
int i;
- int common_modes[AMDGPU_BENCHMARK_COMMON_MODES_N] = {
+ static const int common_modes[AMDGPU_BENCHMARK_COMMON_MODES_N] = {
640 * 480 * 4,
720 * 480 * 4,
800 * 600 * 4,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
index 119cdc2..60a0c9a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
@@ -439,7 +439,7 @@ static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
struct drm_display_mode *mode = NULL;
struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
int i;
- struct mode_size {
+ static const struct mode_size {
int w;
int h;
} common_modes[17] = {
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h
index b10df32..009bd59 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h
@@ -127,8 +127,8 @@ fInt fExponential(fInt exponent) /*Can be used to calculate e^exponent*/
fInt solution = fPositiveOne; /*Starting off with baseline of 1 */
fInt error_term;
- uint32_t k_array[11] = {55452, 27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78};
- uint32_t expk_array[11] = {2560000, 160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078};
+ static const uint32_t k_array[11] = {55452, 27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78};
+ static const uint32_t expk_array[11] = {2560000, 160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078};
if (GreaterThan(fZERO, exponent)) {
exponent = fNegate(exponent);
@@ -162,8 +162,8 @@ fInt fNaturalLog(fInt value)
fInt solution = ConvertToFraction(0); /*Starting off with baseline of 0 */
fInt error_term;
- uint32_t k_array[10] = {160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078};
- uint32_t logk_array[10] = {27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78};
+ static const uint32_t k_array[10] = {160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078};
+ static const uint32_t logk_array[10] = {27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78};
while (GreaterThan(fAdd(value, fNegativeOne), upper_bound)) {
for (i = 0; i < 10; i++) {
--
2.8.0.rc3
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/6] drm/amd: Mark some tables as const
2016-04-10 14:29 [PATCH 1/6] drm/amd: Mark some tables as const Nils Wallménius
` (4 preceding siblings ...)
2016-04-10 14:30 ` [PATCH 6/6] drm/amd: make some function-local tables static const Nils Wallménius
@ 2016-04-11 7:32 ` Christian König
2016-04-11 17:07 ` Alex Deucher
5 siblings, 1 reply; 8+ messages in thread
From: Christian König @ 2016-04-11 7:32 UTC (permalink / raw
To: Nils Wallménius, dri-devel
Am 10.04.2016 um 16:29 schrieb Nils Wallménius:
> This patch marks some compile-time constant tables 'const'.
> The tables marked in this patch are the low hanging fruit
> where little other changes were necesary to avoid casting
> away constness etc. Also mark some tables that are private
> to a file as static.
>
> Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
Nice cleanup, for the series Reviewed-by: Christian König
<christian.koenig@amd.com>
Thanks,
Christian.
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
> drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 12 ++++++------
> drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h | 2 +-
> drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c | 10 +++++-----
> drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 8 ++++----
> drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h | 2 +-
> drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c | 2 +-
> drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 6 +++---
> drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 2 +-
> 13 files changed, 29 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 66e51f9..5d05b5d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -2348,7 +2348,7 @@ static inline void amdgpu_unregister_atpx_handler(void) {}
> * KMS
> */
> extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
> -extern int amdgpu_max_kms_ioctl;
> +extern const int amdgpu_max_kms_ioctl;
>
> int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
> int amdgpu_driver_unload_kms(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index 0535095..c835abe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -596,20 +596,20 @@ const struct drm_mode_config_funcs amdgpu_mode_funcs = {
> .output_poll_changed = amdgpu_output_poll_changed
> };
>
> -static struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
> +static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
> { { UNDERSCAN_OFF, "off" },
> { UNDERSCAN_ON, "on" },
> { UNDERSCAN_AUTO, "auto" },
> };
>
> -static struct drm_prop_enum_list amdgpu_audio_enum_list[] =
> +static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
> { { AMDGPU_AUDIO_DISABLE, "off" },
> { AMDGPU_AUDIO_ENABLE, "on" },
> { AMDGPU_AUDIO_AUTO, "auto" },
> };
>
> /* XXX support different dither options? spatial, temporal, both, etc. */
> -static struct drm_prop_enum_list amdgpu_dither_enum_list[] =
> +static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
> { { AMDGPU_FMT_DITHER_DISABLE, "off" },
> { AMDGPU_FMT_DITHER_ENABLE, "on" },
> };
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index f1e17d6..2d9dbc2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -166,7 +166,7 @@ module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
> MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
> module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
>
> -static struct pci_device_id pciidlist[] = {
> +static const struct pci_device_id pciidlist[] = {
> #ifdef CONFIG_DRM_AMDGPU_CIK
> /* Kaveri */
> {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> index 762cfdb..9266c7b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> @@ -498,7 +498,7 @@ static int amdgpu_irqdomain_map(struct irq_domain *d,
> return 0;
> }
>
> -static struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
> +static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
> .map = amdgpu_irqdomain_map,
> };
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 7805a87..1f9d318 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -754,4 +754,4 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
> DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> };
> -int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
> +const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
> index 025a3ed..55a006d 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
> @@ -95,23 +95,23 @@ enum DPM_EVENT_SRC {
> /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
> * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
> */
> -uint16_t fiji_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0},
> - {600, 1050, 6, 1} };
> +static const uint16_t fiji_clock_stretcher_lookup_table[2][4] =
> +{ {600, 1050, 3, 0}, {600, 1050, 6, 1} };
>
> /* [FF, SS] type, [] 4 voltage ranges, and
> * [Floor Freq, Boundary Freq, VID min , VID max]
> */
> -uint32_t fiji_clock_stretcher_ddt_table[2][4][4] =
> +static const uint32_t fiji_clock_stretcher_ddt_table[2][4][4] =
> { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
> { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
>
> /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
> * (coming from PWR_CKS_CNTL.stretch_amount reg spec)
> */
> -uint8_t fiji_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5},
> - {0, 2, 4, 5, 6, 5} };
> +static const uint8_t fiji_clock_stretch_amount_conversion[2][6] =
> +{ {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
>
> -const unsigned long PhwFiji_Magic = (unsigned long)(PHM_VIslands_Magic);
> +static const unsigned long PhwFiji_Magic = (unsigned long)(PHM_VIslands_Magic);
>
> struct fiji_power_state *cast_phw_fiji_power_state(
> struct pp_hw_power_state *hw_ps)
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
> index a16f7cd..4b29d9e 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
> @@ -263,7 +263,7 @@ struct fiji_hwmgr {
> bool enable_tdc_limit_feature;
> bool enable_pkg_pwr_tracking_feature;
> bool disable_uvd_power_tune_feature;
> - struct fiji_pt_defaults *power_tune_defaults;
> + const struct fiji_pt_defaults *power_tune_defaults;
> struct SMU73_Discrete_PmFuses power_tune_table;
> uint32_t dte_tj_offset;
> uint32_t fast_watermark_threshold;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
> index 6efcb2b..db23a40 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
> @@ -32,7 +32,7 @@
> #define VOLTAGE_SCALE 4
> #define POWERTUNE_DEFAULT_SET_MAX 1
>
> -struct fiji_pt_defaults fiji_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
> +const struct fiji_pt_defaults fiji_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
> /*sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc */
> {1, 0xF, 0xFD,
> /* TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase */
> @@ -143,7 +143,7 @@ static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t* sda)
> int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
> {
> struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
> - struct fiji_pt_defaults *defaults = data->power_tune_defaults;
> + const struct fiji_pt_defaults *defaults = data->power_tune_defaults;
> SMU73_Discrete_DpmTable *dpm_table = &(data->smc_state_table);
> struct phm_ppt_v1_information *table_info =
> (struct phm_ppt_v1_information *)(hwmgr->pptable);
> @@ -222,7 +222,7 @@ int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
> static int fiji_populate_svi_load_line(struct pp_hwmgr *hwmgr)
> {
> struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
> - struct fiji_pt_defaults *defaults = data->power_tune_defaults;
> + const struct fiji_pt_defaults *defaults = data->power_tune_defaults;
>
> data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
> data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
> @@ -238,7 +238,7 @@ static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr)
> struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
> struct phm_ppt_v1_information *table_info =
> (struct phm_ppt_v1_information *)(hwmgr->pptable);
> - struct fiji_pt_defaults *defaults = data->power_tune_defaults;
> + const struct fiji_pt_defaults *defaults = data->power_tune_defaults;
>
> /* TDC number of fraction bits are changed from 8 to 7
> * for Fiji as requested by SMC team
> @@ -256,7 +256,7 @@ static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr)
> static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
> {
> struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
> - struct fiji_pt_defaults *defaults = data->power_tune_defaults;
> + const struct fiji_pt_defaults *defaults = data->power_tune_defaults;
> uint32_t temp;
>
> if (fiji_read_smc_sram_dword(hwmgr->smumgr,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
> index fee7835..2e99a14 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
> @@ -86,17 +86,17 @@
> typedef uint32_t PECI_RegistryValue;
>
> /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */
> -uint16_t PP_ClockStretcherLookupTable[2][4] = {
> +static const uint16_t PP_ClockStretcherLookupTable[2][4] = {
> {600, 1050, 3, 0},
> {600, 1050, 6, 1} };
>
> /* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
> -uint32_t PP_ClockStretcherDDTTable[2][4][4] = {
> +static const uint32_t PP_ClockStretcherDDTTable[2][4][4] = {
> { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
> { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
>
> /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
> -uint8_t PP_ClockStretchAmountConversion[2][6] = {
> +static const uint8_t PP_ClockStretchAmountConversion[2][6] = {
> {0, 1, 3, 2, 4, 5},
> {0, 2, 4, 5, 6, 5} };
>
> @@ -110,7 +110,7 @@ enum DPM_EVENT_SRC {
> };
> typedef enum DPM_EVENT_SRC DPM_EVENT_SRC;
>
> -const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic);
> +static const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic);
>
> struct tonga_power_state *cast_phw_tonga_power_state(
> struct pp_hw_power_state *hw_ps)
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
> index 0262ad3..8a31665 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
> @@ -46,7 +46,7 @@ struct PWR_Command_Table
> typedef struct PWR_Command_Table PWR_Command_Table;
>
> #define PWR_VIRUS_TABLE_SIZE 10243
> -static PWR_Command_Table PwrVirusTable[PWR_VIRUS_TABLE_SIZE] =
> +static const PWR_Command_Table PwrVirusTable[PWR_VIRUS_TABLE_SIZE] =
> {
> { PwrCmdWrite, 0x100100b6, mmPCIE_INDEX },
> { PwrCmdWrite, 0x00000000, mmPCIE_DATA },
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
> index ec222c6..da18f44 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
> @@ -39,7 +39,7 @@
>
> #define SIZE_ALIGN_32(x) (((x) + 31) / 32 * 32)
>
> -static enum cz_scratch_entry firmware_list[] = {
> +static const enum cz_scratch_entry firmware_list[] = {
> CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0,
> CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1,
> CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE,
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> index cdbb9f8..673a75c 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> @@ -44,7 +44,7 @@
>
> #define FIJI_SMC_SIZE 0x20000
>
> -struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] = {
> +static const struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] = {
> /* Min Sclk pcie DeepSleep Activity CgSpll CgSpll spllSpread SpllSpread CcPwr CcPwr Sclk Display Enabled Enabled Voltage Power */
> /* Voltage, Frequency, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, Spectrum, Spectrum2, DynRm, DynRm1 Did, Watermark, ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
> { 0x3c0fd047, 0x30750000, 0x00, 0x03, 0x1e00, 0x00200410, 0x87020000, 0x21680000, 0x0c000000, 0, 0, 0x16, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 },
> @@ -189,7 +189,7 @@ int fiji_copy_bytes_to_smc(struct pp_smumgr *smumgr,
>
> int fiji_program_jump_on_start(struct pp_smumgr *smumgr)
> {
> - static unsigned char data[] = { 0xE0, 0x00, 0x80, 0x40 };
> + static const unsigned char data[] = { 0xE0, 0x00, 0x80, 0x40 };
>
> fiji_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data) + 1);
>
> @@ -665,7 +665,7 @@ int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
> {
> int i, result = -1;
> uint32_t reg, data;
> - PWR_Command_Table *virus = PwrVirusTable;
> + const PWR_Command_Table *virus = PwrVirusTable;
> struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
>
> priv->avfs.AvfsBtcStatus = AVFS_LOAD_VIRUS;
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> index ebdb43a..32820b6 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> @@ -145,7 +145,7 @@ out:
>
> int tonga_program_jump_on_start(struct pp_smumgr *smumgr)
> {
> - static unsigned char pData[] = { 0xE0, 0x00, 0x80, 0x40 };
> + static const unsigned char pData[] = { 0xE0, 0x00, 0x80, 0x40 };
>
> tonga_copy_bytes_to_smc(smumgr, 0x0, pData, 4, sizeof(pData)+1);
>
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/6] drm/amd: Mark some tables as const
2016-04-11 7:32 ` [PATCH 1/6] drm/amd: Mark some tables as const Christian König
@ 2016-04-11 17:07 ` Alex Deucher
0 siblings, 0 replies; 8+ messages in thread
From: Alex Deucher @ 2016-04-11 17:07 UTC (permalink / raw
To: Christian König; +Cc: Nils Wallménius, Maling list - DRI developers
On Mon, Apr 11, 2016 at 3:32 AM, Christian König
<deathsimple@vodafone.de> wrote:
> Am 10.04.2016 um 16:29 schrieb Nils Wallménius:
>>
>> This patch marks some compile-time constant tables 'const'.
>> The tables marked in this patch are the low hanging fruit
>> where little other changes were necesary to avoid casting
>> away constness etc. Also mark some tables that are private
>> to a file as static.
>>
>> Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
>
>
> Nice cleanup, for the series Reviewed-by: Christian König
> <christian.koenig@amd.com>
Applied the series.
Thanks,
Alex
>
> Thanks,
> Christian.
>
>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
>> drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 12 ++++++------
>> drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h | 2 +-
>> drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c | 10 +++++-----
>> drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 8 ++++----
>> drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h | 2 +-
>> drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c | 2 +-
>> drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 6 +++---
>> drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 2 +-
>> 13 files changed, 29 insertions(+), 29 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index 66e51f9..5d05b5d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -2348,7 +2348,7 @@ static inline void
>> amdgpu_unregister_atpx_handler(void) {}
>> * KMS
>> */
>> extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
>> -extern int amdgpu_max_kms_ioctl;
>> +extern const int amdgpu_max_kms_ioctl;
>> int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long
>> flags);
>> int amdgpu_driver_unload_kms(struct drm_device *dev);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> index 0535095..c835abe 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> @@ -596,20 +596,20 @@ const struct drm_mode_config_funcs amdgpu_mode_funcs
>> = {
>> .output_poll_changed = amdgpu_output_poll_changed
>> };
>> -static struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
>> +static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
>> { { UNDERSCAN_OFF, "off" },
>> { UNDERSCAN_ON, "on" },
>> { UNDERSCAN_AUTO, "auto" },
>> };
>> -static struct drm_prop_enum_list amdgpu_audio_enum_list[] =
>> +static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
>> { { AMDGPU_AUDIO_DISABLE, "off" },
>> { AMDGPU_AUDIO_ENABLE, "on" },
>> { AMDGPU_AUDIO_AUTO, "auto" },
>> };
>> /* XXX support different dither options? spatial, temporal, both, etc.
>> */
>> -static struct drm_prop_enum_list amdgpu_dither_enum_list[] =
>> +static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
>> { { AMDGPU_FMT_DITHER_DISABLE, "off" },
>> { AMDGPU_FMT_DITHER_ENABLE, "on" },
>> };
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> index f1e17d6..2d9dbc2 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> @@ -166,7 +166,7 @@ module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap,
>> uint, 0444);
>> MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect
>> (default))");
>> module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
>> -static struct pci_device_id pciidlist[] = {
>> +static const struct pci_device_id pciidlist[] = {
>> #ifdef CONFIG_DRM_AMDGPU_CIK
>> /* Kaveri */
>> {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
>> CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>> index 762cfdb..9266c7b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>> @@ -498,7 +498,7 @@ static int amdgpu_irqdomain_map(struct irq_domain *d,
>> return 0;
>> }
>> -static struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
>> +static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
>> .map = amdgpu_irqdomain_map,
>> };
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> index 7805a87..1f9d318 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> @@ -754,4 +754,4 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
>> DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl,
>> DRM_AUTH|DRM_RENDER_ALLOW),
>> DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl,
>> DRM_AUTH|DRM_RENDER_ALLOW),
>> };
>> -int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
>> +const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
>> index 025a3ed..55a006d 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
>> @@ -95,23 +95,23 @@ enum DPM_EVENT_SRC {
>> /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
>> * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
>> */
>> -uint16_t fiji_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0},
>> - {600, 1050, 6, 1} };
>> +static const uint16_t fiji_clock_stretcher_lookup_table[2][4] =
>> +{ {600, 1050, 3, 0}, {600, 1050, 6, 1} };
>> /* [FF, SS] type, [] 4 voltage ranges, and
>> * [Floor Freq, Boundary Freq, VID min , VID max]
>> */
>> -uint32_t fiji_clock_stretcher_ddt_table[2][4][4] =
>> +static const uint32_t fiji_clock_stretcher_ddt_table[2][4][4] =
>> { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0,
>> 0, 0, 31} },
>> { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384,
>> 768, 32, 63} } };
>> /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
>> * (coming from PWR_CKS_CNTL.stretch_amount reg spec)
>> */
>> -uint8_t fiji_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4,
>> 5},
>> - {0, 2, 4, 5, 6, 5} };
>> +static const uint8_t fiji_clock_stretch_amount_conversion[2][6] =
>> +{ {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
>> -const unsigned long PhwFiji_Magic = (unsigned
>> long)(PHM_VIslands_Magic);
>> +static const unsigned long PhwFiji_Magic = (unsigned
>> long)(PHM_VIslands_Magic);
>> struct fiji_power_state *cast_phw_fiji_power_state(
>> struct pp_hw_power_state *hw_ps)
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
>> index a16f7cd..4b29d9e 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
>> @@ -263,7 +263,7 @@ struct fiji_hwmgr {
>> bool enable_tdc_limit_feature;
>> bool enable_pkg_pwr_tracking_feature;
>> bool disable_uvd_power_tune_feature;
>> - struct fiji_pt_defaults *power_tune_defaults;
>> + const struct fiji_pt_defaults *power_tune_defaults;
>> struct SMU73_Discrete_PmFuses power_tune_table;
>> uint32_t dte_tj_offset;
>> uint32_t fast_watermark_threshold;
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
>> index 6efcb2b..db23a40 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
>> @@ -32,7 +32,7 @@
>> #define VOLTAGE_SCALE 4
>> #define POWERTUNE_DEFAULT_SET_MAX 1
>> -struct fiji_pt_defaults
>> fiji_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
>> +const struct fiji_pt_defaults
>> fiji_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
>> /*sviLoadLIneEn, SviLoadLineVddC,
>> TDC_VDDC_ThrottleReleaseLimitPerc */
>> {1, 0xF, 0xFD,
>> /* TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase */
>> @@ -143,7 +143,7 @@ static void get_scl_sda_value(uint8_t line, uint8_t
>> *scl, uint8_t* sda)
>> int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
>> {
>> struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
>> - struct fiji_pt_defaults *defaults = data->power_tune_defaults;
>> + const struct fiji_pt_defaults *defaults =
>> data->power_tune_defaults;
>> SMU73_Discrete_DpmTable *dpm_table = &(data->smc_state_table);
>> struct phm_ppt_v1_information *table_info =
>> (struct phm_ppt_v1_information *)(hwmgr->pptable);
>> @@ -222,7 +222,7 @@ int fiji_populate_bapm_parameters_in_dpm_table(struct
>> pp_hwmgr *hwmgr)
>> static int fiji_populate_svi_load_line(struct pp_hwmgr *hwmgr)
>> {
>> struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
>> - struct fiji_pt_defaults *defaults = data->power_tune_defaults;
>> + const struct fiji_pt_defaults *defaults = data->power_tune_defaults;
>> data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
>> data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
>> @@ -238,7 +238,7 @@ static int fiji_populate_tdc_limit(struct pp_hwmgr
>> *hwmgr)
>> struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
>> struct phm_ppt_v1_information *table_info =
>> (struct phm_ppt_v1_information *)(hwmgr->pptable);
>> - struct fiji_pt_defaults *defaults = data->power_tune_defaults;
>> + const struct fiji_pt_defaults *defaults =
>> data->power_tune_defaults;
>> /* TDC number of fraction bits are changed from 8 to 7
>> * for Fiji as requested by SMC team
>> @@ -256,7 +256,7 @@ static int fiji_populate_tdc_limit(struct pp_hwmgr
>> *hwmgr)
>> static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t
>> fuse_table_offset)
>> {
>> struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
>> - struct fiji_pt_defaults *defaults = data->power_tune_defaults;
>> + const struct fiji_pt_defaults *defaults =
>> data->power_tune_defaults;
>> uint32_t temp;
>> if (fiji_read_smc_sram_dword(hwmgr->smumgr,
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
>> index fee7835..2e99a14 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
>> @@ -86,17 +86,17 @@
>> typedef uint32_t PECI_RegistryValue;
>> /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs not and [Fmin,
>> Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */
>> -uint16_t PP_ClockStretcherLookupTable[2][4] = {
>> +static const uint16_t PP_ClockStretcherLookupTable[2][4] = {
>> {600, 1050, 3, 0},
>> {600, 1050, 6, 1} };
>> /* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq,
>> VID min , VID max] */
>> -uint32_t PP_ClockStretcherDDTTable[2][4][4] = {
>> +static const uint32_t PP_ClockStretcherDDTTable[2][4][4] = {
>> { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95},
>> {0, 0, 0, 31} },
>> { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95},
>> {384, 768, 32, 63} } };
>> /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming
>> from PWR_CKS_CNTL.stretch_amount reg spec) */
>> -uint8_t PP_ClockStretchAmountConversion[2][6] = {
>> +static const uint8_t PP_ClockStretchAmountConversion[2][6] = {
>> {0, 1, 3, 2, 4, 5},
>> {0, 2, 4, 5, 6, 5} };
>> @@ -110,7 +110,7 @@ enum DPM_EVENT_SRC {
>> };
>> typedef enum DPM_EVENT_SRC DPM_EVENT_SRC;
>> -const unsigned long PhwTonga_Magic = (unsigned
>> long)(PHM_VIslands_Magic);
>> +static const unsigned long PhwTonga_Magic = (unsigned
>> long)(PHM_VIslands_Magic);
>> struct tonga_power_state *cast_phw_tonga_power_state(
>> struct pp_hw_power_state *hw_ps)
>> diff --git a/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
>> b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
>> index 0262ad3..8a31665 100644
>> --- a/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
>> +++ b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
>> @@ -46,7 +46,7 @@ struct PWR_Command_Table
>> typedef struct PWR_Command_Table PWR_Command_Table;
>> #define PWR_VIRUS_TABLE_SIZE 10243
>> -static PWR_Command_Table PwrVirusTable[PWR_VIRUS_TABLE_SIZE] =
>> +static const PWR_Command_Table PwrVirusTable[PWR_VIRUS_TABLE_SIZE] =
>> {
>> { PwrCmdWrite, 0x100100b6, mmPCIE_INDEX
>> },
>> { PwrCmdWrite, 0x00000000, mmPCIE_DATA
>> },
>> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
>> b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
>> index ec222c6..da18f44 100644
>> --- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
>> @@ -39,7 +39,7 @@
>> #define SIZE_ALIGN_32(x) (((x) + 31) / 32 * 32)
>> -static enum cz_scratch_entry firmware_list[] = {
>> +static const enum cz_scratch_entry firmware_list[] = {
>> CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0,
>> CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1,
>> CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE,
>> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
>> b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
>> index cdbb9f8..673a75c 100644
>> --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
>> @@ -44,7 +44,7 @@
>> #define FIJI_SMC_SIZE 0x20000
>> -struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] = {
>> +static const struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] =
>> {
>> /* Min Sclk pcie DeepSleep Activity
>> CgSpll CgSpll spllSpread SpllSpread CcPwr CcPwr Sclk Display
>> Enabled Enabled Voltage Power */
>> /* Voltage, Frequency, DpmLevel, DivId, Level,
>> FuncCntl3, FuncCntl4, Spectrum, Spectrum2, DynRm, DynRm1 Did,
>> Watermark, ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
>> { 0x3c0fd047, 0x30750000, 0x00, 0x03, 0x1e00,
>> 0x00200410, 0x87020000, 0x21680000, 0x0c000000, 0, 0, 0x16, 0x00,
>> 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 },
>> @@ -189,7 +189,7 @@ int fiji_copy_bytes_to_smc(struct pp_smumgr *smumgr,
>> int fiji_program_jump_on_start(struct pp_smumgr *smumgr)
>> {
>> - static unsigned char data[] = { 0xE0, 0x00, 0x80, 0x40 };
>> + static const unsigned char data[] = { 0xE0, 0x00, 0x80, 0x40 };
>> fiji_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data) + 1);
>> @@ -665,7 +665,7 @@ int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
>> {
>> int i, result = -1;
>> uint32_t reg, data;
>> - PWR_Command_Table *virus = PwrVirusTable;
>> + const PWR_Command_Table *virus = PwrVirusTable;
>> struct fiji_smumgr *priv = (struct fiji_smumgr
>> *)(smumgr->backend);
>> priv->avfs.AvfsBtcStatus = AVFS_LOAD_VIRUS;
>> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
>> b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
>> index ebdb43a..32820b6 100644
>> --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
>> @@ -145,7 +145,7 @@ out:
>> int tonga_program_jump_on_start(struct pp_smumgr *smumgr)
>> {
>> - static unsigned char pData[] = { 0xE0, 0x00, 0x80, 0x40 };
>> + static const unsigned char pData[] = { 0xE0, 0x00, 0x80, 0x40 };
>> tonga_copy_bytes_to_smc(smumgr, 0x0, pData, 4, sizeof(pData)+1);
>>
>
>
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2016-04-11 17:07 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-04-10 14:29 [PATCH 1/6] drm/amd: Mark some tables as const Nils Wallménius
2016-04-10 14:30 ` [PATCH 2/6] drm/amd/scheduler: Mark amdgpu_sched_ops const Nils Wallménius
2016-04-10 14:30 ` [PATCH 3/6] drm/amdgpu: Mark all instances of struct drm_info_list as const Nils Wallménius
2016-04-10 14:30 ` [PATCH 4/6] drm/amd/powerplay: Mark pem_event_action chains " Nils Wallménius
2016-04-10 14:30 ` [PATCH 5/6] drm/amd/powerplay: mark phm_master_table_* structs " Nils Wallménius
2016-04-10 14:30 ` [PATCH 6/6] drm/amd: make some function-local tables static const Nils Wallménius
2016-04-11 7:32 ` [PATCH 1/6] drm/amd: Mark some tables as const Christian König
2016-04-11 17:07 ` Alex Deucher
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