* [PATCH v4 0/6] this is the 1st version of suspend. RK3288 can shut down the cpu, gpu and
@ 2014-10-21 23:17 ` Chris Zhong
0 siblings, 0 replies; 39+ messages in thread
From: Chris Zhong @ 2014-10-21 23:17 UTC (permalink / raw
To: Heiko Stuebner
Cc: Mike Turquette, Ian Campbell, dianders, devicetree, linux-kernel,
Kumar Gala, Russell King, linux-rockchip, Rob Herring, Pawel Moll,
Chris Zhong, Mark Rutland, linux-arm-kernel, Linus Walleij
other device controllers in suspend, and it will pull the GLOBAL_PWROFF pin
to high in the final stage of the process of suspend, pull the pin to low again
when resume.
Changes in v4:
- use SIMPLE_DE_PM_OPS for suspend/resume struct
- remove grf regmap
Changes in v3:
- move the pinmux of gpio6_c6 save and restore to pinctrl-rockchip
Changes in v2:
- __raw_readl/__raw_writel replaced by readl_relaxed/writel_relaxed
- add the regulator calls in prepare and finish.
- add the pinmux of gpio6_c6 save and restore
- put "rockchip,rk3288-pmu-sram" to first
Chris (1):
pinctrl: rockchip: add suspend/resume functions
Chris Zhong (5):
pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume
clk: rockchip: RK3288: add suspend and resume
ARM: rockchip: add suspend and resume for RK3288
ARM: rockchip: Add pmu-sram binding
ARM: dts: add RK3288 suspend support
.../devicetree/bindings/arm/rockchip/pmu-sram.txt | 15 +
arch/arm/boot/dts/rk3288.dtsi | 11 +
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/pm.c | 307 ++++++++++++++++++++
arch/arm/mach-rockchip/pm.h | 102 +++++++
arch/arm/mach-rockchip/rockchip.c | 11 +-
arch/arm/mach-rockchip/sleep.S | 87 ++++++
drivers/clk/rockchip/clk-rk3288.c | 63 ++++
drivers/pinctrl/pinctrl-rockchip.c | 47 +++
9 files changed, 642 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
create mode 100644 arch/arm/mach-rockchip/pm.c
create mode 100644 arch/arm/mach-rockchip/pm.h
create mode 100644 arch/arm/mach-rockchip/sleep.S
--
1.7.9.5
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v4 0/6] this is the 1st version of suspend. RK3288 can shut down the cpu, gpu and
@ 2014-10-21 23:17 ` Chris Zhong
0 siblings, 0 replies; 39+ messages in thread
From: Chris Zhong @ 2014-10-21 23:17 UTC (permalink / raw
To: linux-arm-kernel
other device controllers in suspend, and it will pull the GLOBAL_PWROFF pin
to high in the final stage of the process of suspend, pull the pin to low again
when resume.
Changes in v4:
- use SIMPLE_DE_PM_OPS for suspend/resume struct
- remove grf regmap
Changes in v3:
- move the pinmux of gpio6_c6 save and restore to pinctrl-rockchip
Changes in v2:
- __raw_readl/__raw_writel replaced by readl_relaxed/writel_relaxed
- add the regulator calls in prepare and finish.
- add the pinmux of gpio6_c6 save and restore
- put "rockchip,rk3288-pmu-sram" to first
Chris (1):
pinctrl: rockchip: add suspend/resume functions
Chris Zhong (5):
pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume
clk: rockchip: RK3288: add suspend and resume
ARM: rockchip: add suspend and resume for RK3288
ARM: rockchip: Add pmu-sram binding
ARM: dts: add RK3288 suspend support
.../devicetree/bindings/arm/rockchip/pmu-sram.txt | 15 +
arch/arm/boot/dts/rk3288.dtsi | 11 +
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/pm.c | 307 ++++++++++++++++++++
arch/arm/mach-rockchip/pm.h | 102 +++++++
arch/arm/mach-rockchip/rockchip.c | 11 +-
arch/arm/mach-rockchip/sleep.S | 87 ++++++
drivers/clk/rockchip/clk-rk3288.c | 63 ++++
drivers/pinctrl/pinctrl-rockchip.c | 47 +++
9 files changed, 642 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
create mode 100644 arch/arm/mach-rockchip/pm.c
create mode 100644 arch/arm/mach-rockchip/pm.h
create mode 100644 arch/arm/mach-rockchip/sleep.S
--
1.7.9.5
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v4 1/6] pinctrl: rockchip: add suspend/resume functions
2014-10-21 23:17 ` Chris Zhong
@ 2014-10-21 23:19 ` Chris Zhong
-1 siblings, 0 replies; 39+ messages in thread
From: Chris Zhong @ 2014-10-21 23:19 UTC (permalink / raw
To: Heiko Stuebner
Cc: Mike Turquette, Ian Campbell, dianders, devicetree, linux-kernel,
Kumar Gala, Russell King, linux-rockchip, Rob Herring, Pawel Moll,
Chris Zhong, Mark Rutland, linux-arm-kernel, Linus Walleij
From: Chris <zyw@rock-chips.com>
support suspend/resume of pinctrl, it allows handling sleep mode
for hogged pins in pinctrl
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---
Changes in v4:
- use SIMPLE_DEV_PM_OPS for suspend/resume struct
Changes in v3: None
Changes in v2: None
drivers/pinctrl/pinctrl-rockchip.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 016f457..c4a988d 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1770,6 +1770,25 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
return ctrl;
}
+#ifdef CONFIG_PM_SLEEP
+static int rockchip_pinctrl_suspend(struct device *dev)
+{
+ struct rockchip_pinctrl *info = dev_get_drvdata(dev);
+
+ return pinctrl_force_sleep(info->pctl_dev);
+}
+
+static int rockchip_pinctrl_resume(struct device *dev)
+{
+ struct rockchip_pinctrl *info = dev_get_drvdata(dev);
+
+ return pinctrl_force_default(info->pctl_dev);
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
+ rockchip_pinctrl_resume);
+
static int rockchip_pinctrl_probe(struct platform_device *pdev)
{
struct rockchip_pinctrl *info;
@@ -1983,6 +2002,7 @@ static struct platform_driver rockchip_pinctrl_driver = {
.driver = {
.name = "rockchip-pinctrl",
.owner = THIS_MODULE,
+ .pm = &rockchip_pinctrl_dev_pm_ops,
.of_match_table = rockchip_pinctrl_dt_match,
},
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v4 1/6] pinctrl: rockchip: add suspend/resume functions
@ 2014-10-21 23:19 ` Chris Zhong
0 siblings, 0 replies; 39+ messages in thread
From: Chris Zhong @ 2014-10-21 23:19 UTC (permalink / raw
To: linux-arm-kernel
From: Chris <zyw@rock-chips.com>
support suspend/resume of pinctrl, it allows handling sleep mode
for hogged pins in pinctrl
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---
Changes in v4:
- use SIMPLE_DEV_PM_OPS for suspend/resume struct
Changes in v3: None
Changes in v2: None
drivers/pinctrl/pinctrl-rockchip.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 016f457..c4a988d 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1770,6 +1770,25 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
return ctrl;
}
+#ifdef CONFIG_PM_SLEEP
+static int rockchip_pinctrl_suspend(struct device *dev)
+{
+ struct rockchip_pinctrl *info = dev_get_drvdata(dev);
+
+ return pinctrl_force_sleep(info->pctl_dev);
+}
+
+static int rockchip_pinctrl_resume(struct device *dev)
+{
+ struct rockchip_pinctrl *info = dev_get_drvdata(dev);
+
+ return pinctrl_force_default(info->pctl_dev);
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
+ rockchip_pinctrl_resume);
+
static int rockchip_pinctrl_probe(struct platform_device *pdev)
{
struct rockchip_pinctrl *info;
@@ -1983,6 +2002,7 @@ static struct platform_driver rockchip_pinctrl_driver = {
.driver = {
.name = "rockchip-pinctrl",
.owner = THIS_MODULE,
+ .pm = &rockchip_pinctrl_dev_pm_ops,
.of_match_table = rockchip_pinctrl_dt_match,
},
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v4 2/6] pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume
@ 2014-10-21 23:19 ` Chris Zhong
0 siblings, 0 replies; 39+ messages in thread
From: Chris Zhong @ 2014-10-21 23:19 UTC (permalink / raw
To: Heiko Stuebner
Cc: Mike Turquette, Ian Campbell, dianders, devicetree, linux-kernel,
Kumar Gala, Russell King, linux-rockchip, Rob Herring, Pawel Moll,
Chris Zhong, Mark Rutland, linux-arm-kernel, Linus Walleij
Save and restore the gpio6_c6 pinmux setting, since Maskrom of RK3288
would modify it to sdmmc0_det, so it need to be restored to the correct
setting after resume from Maskrom.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/pinctrl/pinctrl-rockchip.c | 29 ++++++++++++++++++++++++++++-
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index c4a988d..e2068fe 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1771,16 +1771,43 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
}
#ifdef CONFIG_PM_SLEEP
+
+#define RK3288_GRF_GPIO6C_IOMUX 0x64
+#define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
+
+static u32 rk3288_grf_gpio6c_iomux;
+
static int rockchip_pinctrl_suspend(struct device *dev)
{
struct rockchip_pinctrl *info = dev_get_drvdata(dev);
+ int ret = pinctrl_force_sleep(info->pctl_dev);
+
+ if (ret)
+ return ret;
+
+ /*
+ * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
+ * the setting here, and restore it at resume.
+ */
+ if (info->ctrl->type == RK3288) {
+ ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
+ &rk3288_grf_gpio6c_iomux);
+ if (ret)
+ return ret;
+ }
- return pinctrl_force_sleep(info->pctl_dev);
+ return 0;
}
static int rockchip_pinctrl_resume(struct device *dev)
{
struct rockchip_pinctrl *info = dev_get_drvdata(dev);
+ int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
+ rk3288_grf_gpio6c_iomux |
+ GPIO6C6_SEL_WRITE_ENABLE);
+
+ if (ret)
+ return ret;
return pinctrl_force_default(info->pctl_dev);
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v4 2/6] pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume
@ 2014-10-21 23:19 ` Chris Zhong
0 siblings, 0 replies; 39+ messages in thread
From: Chris Zhong @ 2014-10-21 23:19 UTC (permalink / raw
To: Heiko Stuebner
Cc: Mike Turquette, Ian Campbell, dianders-F7+t8E8rja9g9hUCZPvPmw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Kumar Gala, Russell King,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring,
Pawel Moll, Chris Zhong, Mark Rutland,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Linus Walleij
Save and restore the gpio6_c6 pinmux setting, since Maskrom of RK3288
would modify it to sdmmc0_det, so it need to be restored to the correct
setting after resume from Maskrom.
Signed-off-by: Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/pinctrl/pinctrl-rockchip.c | 29 ++++++++++++++++++++++++++++-
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index c4a988d..e2068fe 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1771,16 +1771,43 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
}
#ifdef CONFIG_PM_SLEEP
+
+#define RK3288_GRF_GPIO6C_IOMUX 0x64
+#define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
+
+static u32 rk3288_grf_gpio6c_iomux;
+
static int rockchip_pinctrl_suspend(struct device *dev)
{
struct rockchip_pinctrl *info = dev_get_drvdata(dev);
+ int ret = pinctrl_force_sleep(info->pctl_dev);
+
+ if (ret)
+ return ret;
+
+ /*
+ * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
+ * the setting here, and restore it at resume.
+ */
+ if (info->ctrl->type == RK3288) {
+ ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
+ &rk3288_grf_gpio6c_iomux);
+ if (ret)
+ return ret;
+ }
- return pinctrl_force_sleep(info->pctl_dev);
+ return 0;
}
static int rockchip_pinctrl_resume(struct device *dev)
{
struct rockchip_pinctrl *info = dev_get_drvdata(dev);
+ int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
+ rk3288_grf_gpio6c_iomux |
+ GPIO6C6_SEL_WRITE_ENABLE);
+
+ if (ret)
+ return ret;
return pinctrl_force_default(info->pctl_dev);
}
--
1.7.9.5
--
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^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v4 2/6] pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume
@ 2014-10-21 23:19 ` Chris Zhong
0 siblings, 0 replies; 39+ messages in thread
From: Chris Zhong @ 2014-10-21 23:19 UTC (permalink / raw
To: linux-arm-kernel
Save and restore the gpio6_c6 pinmux setting, since Maskrom of RK3288
would modify it to sdmmc0_det, so it need to be restored to the correct
setting after resume from Maskrom.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/pinctrl/pinctrl-rockchip.c | 29 ++++++++++++++++++++++++++++-
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index c4a988d..e2068fe 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1771,16 +1771,43 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
}
#ifdef CONFIG_PM_SLEEP
+
+#define RK3288_GRF_GPIO6C_IOMUX 0x64
+#define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
+
+static u32 rk3288_grf_gpio6c_iomux;
+
static int rockchip_pinctrl_suspend(struct device *dev)
{
struct rockchip_pinctrl *info = dev_get_drvdata(dev);
+ int ret = pinctrl_force_sleep(info->pctl_dev);
+
+ if (ret)
+ return ret;
+
+ /*
+ * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
+ * the setting here, and restore it at resume.
+ */
+ if (info->ctrl->type == RK3288) {
+ ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
+ &rk3288_grf_gpio6c_iomux);
+ if (ret)
+ return ret;
+ }
- return pinctrl_force_sleep(info->pctl_dev);
+ return 0;
}
static int rockchip_pinctrl_resume(struct device *dev)
{
struct rockchip_pinctrl *info = dev_get_drvdata(dev);
+ int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
+ rk3288_grf_gpio6c_iomux |
+ GPIO6C6_SEL_WRITE_ENABLE);
+
+ if (ret)
+ return ret;
return pinctrl_force_default(info->pctl_dev);
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v4 3/6] clk: rockchip: RK3288: add suspend and resume
@ 2014-10-21 23:25 ` Chris Zhong
0 siblings, 0 replies; 39+ messages in thread
From: Chris Zhong @ 2014-10-21 23:25 UTC (permalink / raw
To: Heiko Stuebner
Cc: Mike Turquette, Ian Campbell, dianders, devicetree, linux-kernel,
Kumar Gala, Russell King, linux-rockchip, Rob Herring, Pawel Moll,
Chris Zhong, Mark Rutland, linux-arm-kernel, Linus Walleij,
Tony Xie
save and restore some clks, which might be changed in suspend.
Signed-off-by: Tony Xie <xxx@rock-chips.com>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- __raw_readl/__raw_writel replaced by readl_relaxed/writel_relaxed
drivers/clk/rockchip/clk-rk3288.c | 63 +++++++++++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 2327829..0731b18 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -16,6 +16,7 @@
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rk3288-cru.h>
#include "clk.h"
@@ -762,6 +763,67 @@ static const char *rk3288_critical_clocks[] __initconst = {
"hclk_peri",
};
+#ifdef CONFIG_PM_SLEEP
+static void __iomem *rk3288_cru_base;
+static const int rk3288_saved_cru_reg_ids[] = {
+ RK3288_MODE_CON,
+ RK3288_CLKSEL_CON(0),
+ RK3288_CLKSEL_CON(1),
+ RK3288_CLKSEL_CON(10),
+ RK3288_CLKSEL_CON(33),
+ RK3288_CLKSEL_CON(37),
+};
+
+static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)];
+
+/*
+ * cru will be set in maskrom when system wake up from fastboot
+ * mode in suspend,
+ * so the operation is saving the changed regs.
+ * The apll/cpll/gpll will be set into slow mode in maskrom.
+ * It is mean that resume code run in 24m quit slowly!
+ * so we must resume these plls as soon as possible.
+ */
+static int rk3288_clk_suspend(void)
+{
+ int i, reg_id;
+
+ for (i = 0; i < ARRAY_SIZE(rk3288_saved_cru_reg_ids); i++) {
+ reg_id = rk3288_saved_cru_reg_ids[i];
+
+ rk3288_saved_cru_regs[i] =
+ readl_relaxed(rk3288_cru_base + reg_id);
+ }
+ return 0;
+}
+
+static void rk3288_clk_resume(void)
+{
+ int i, reg_id;
+
+ for (i = ARRAY_SIZE(rk3288_saved_cru_reg_ids) - 1; i >= 0; i--) {
+ reg_id = rk3288_saved_cru_reg_ids[i];
+
+ writel_relaxed(rk3288_saved_cru_regs[i] | 0xffff0000,
+ rk3288_cru_base + reg_id);
+ }
+}
+
+static struct syscore_ops rk3288_clk_syscore_ops = {
+ .suspend = rk3288_clk_suspend,
+ .resume = rk3288_clk_resume,
+};
+
+static void rk3288_clk_sleep_init(void __iomem *reg_base)
+{
+ rk3288_cru_base = reg_base;
+ register_syscore_ops(&rk3288_clk_syscore_ops);
+}
+
+#else /* CONFIG_PM_SLEEP */
+static void rk3288_clk_sleep_init(void __iomem *reg_base) {}
+#endif
+
static void __init rk3288_clk_init(struct device_node *np)
{
void __iomem *reg_base;
@@ -810,5 +872,6 @@ static void __init rk3288_clk_init(struct device_node *np)
ROCKCHIP_SOFTRST_HIWORD_MASK);
rockchip_register_restart_notifier(RK3288_GLB_SRST_FST);
+ rk3288_clk_sleep_init(reg_base);
}
CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v4 3/6] clk: rockchip: RK3288: add suspend and resume
@ 2014-10-21 23:25 ` Chris Zhong
0 siblings, 0 replies; 39+ messages in thread
From: Chris Zhong @ 2014-10-21 23:25 UTC (permalink / raw
To: Heiko Stuebner
Cc: Mike Turquette, Ian Campbell, dianders-F7+t8E8rja9g9hUCZPvPmw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Kumar Gala, Russell King,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring,
Pawel Moll, Chris Zhong, Mark Rutland,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Linus Walleij,
Tony Xie
save and restore some clks, which might be changed in suspend.
Signed-off-by: Tony Xie <xxx-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- __raw_readl/__raw_writel replaced by readl_relaxed/writel_relaxed
drivers/clk/rockchip/clk-rk3288.c | 63 +++++++++++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 2327829..0731b18 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -16,6 +16,7 @@
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rk3288-cru.h>
#include "clk.h"
@@ -762,6 +763,67 @@ static const char *rk3288_critical_clocks[] __initconst = {
"hclk_peri",
};
+#ifdef CONFIG_PM_SLEEP
+static void __iomem *rk3288_cru_base;
+static const int rk3288_saved_cru_reg_ids[] = {
+ RK3288_MODE_CON,
+ RK3288_CLKSEL_CON(0),
+ RK3288_CLKSEL_CON(1),
+ RK3288_CLKSEL_CON(10),
+ RK3288_CLKSEL_CON(33),
+ RK3288_CLKSEL_CON(37),
+};
+
+static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)];
+
+/*
+ * cru will be set in maskrom when system wake up from fastboot
+ * mode in suspend,
+ * so the operation is saving the changed regs.
+ * The apll/cpll/gpll will be set into slow mode in maskrom.
+ * It is mean that resume code run in 24m quit slowly!
+ * so we must resume these plls as soon as possible.
+ */
+static int rk3288_clk_suspend(void)
+{
+ int i, reg_id;
+
+ for (i = 0; i < ARRAY_SIZE(rk3288_saved_cru_reg_ids); i++) {
+ reg_id = rk3288_saved_cru_reg_ids[i];
+
+ rk3288_saved_cru_regs[i] =
+ readl_relaxed(rk3288_cru_base + reg_id);
+ }
+ return 0;
+}
+
+static void rk3288_clk_resume(void)
+{
+ int i, reg_id;
+
+ for (i = ARRAY_SIZE(rk3288_saved_cru_reg_ids) - 1; i >= 0; i--) {
+ reg_id = rk3288_saved_cru_reg_ids[i];
+
+ writel_relaxed(rk3288_saved_cru_regs[i] | 0xffff0000,
+ rk3288_cru_base + reg_id);
+ }
+}
+
+static struct syscore_ops rk3288_clk_syscore_ops = {
+ .suspend = rk3288_clk_suspend,
+ .resume = rk3288_clk_resume,
+};
+
+static void rk3288_clk_sleep_init(void __iomem *reg_base)
+{
+ rk3288_cru_base = reg_base;
+ register_syscore_ops(&rk3288_clk_syscore_ops);
+}
+
+#else /* CONFIG_PM_SLEEP */
+static void rk3288_clk_sleep_init(void __iomem *reg_base) {}
+#endif
+
static void __init rk3288_clk_init(struct device_node *np)
{
void __iomem *reg_base;
@@ -810,5 +872,6 @@ static void __init rk3288_clk_init(struct device_node *np)
ROCKCHIP_SOFTRST_HIWORD_MASK);
rockchip_register_restart_notifier(RK3288_GLB_SRST_FST);
+ rk3288_clk_sleep_init(reg_base);
}
CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
--
1.7.9.5
--
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^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v4 3/6] clk: rockchip: RK3288: add suspend and resume
@ 2014-10-21 23:25 ` Chris Zhong
0 siblings, 0 replies; 39+ messages in thread
From: Chris Zhong @ 2014-10-21 23:25 UTC (permalink / raw
To: linux-arm-kernel
save and restore some clks, which might be changed in suspend.
Signed-off-by: Tony Xie <xxx@rock-chips.com>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- __raw_readl/__raw_writel replaced by readl_relaxed/writel_relaxed
drivers/clk/rockchip/clk-rk3288.c | 63 +++++++++++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 2327829..0731b18 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -16,6 +16,7 @@
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rk3288-cru.h>
#include "clk.h"
@@ -762,6 +763,67 @@ static const char *rk3288_critical_clocks[] __initconst = {
"hclk_peri",
};
+#ifdef CONFIG_PM_SLEEP
+static void __iomem *rk3288_cru_base;
+static const int rk3288_saved_cru_reg_ids[] = {
+ RK3288_MODE_CON,
+ RK3288_CLKSEL_CON(0),
+ RK3288_CLKSEL_CON(1),
+ RK3288_CLKSEL_CON(10),
+ RK3288_CLKSEL_CON(33),
+ RK3288_CLKSEL_CON(37),
+};
+
+static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)];
+
+/*
+ * cru will be set in maskrom when system wake up from fastboot
+ * mode in suspend,
+ * so the operation is saving the changed regs.
+ * The apll/cpll/gpll will be set into slow mode in maskrom.
+ * It is mean that resume code run in 24m quit slowly!
+ * so we must resume these plls as soon as possible.
+ */
+static int rk3288_clk_suspend(void)
+{
+ int i, reg_id;
+
+ for (i = 0; i < ARRAY_SIZE(rk3288_saved_cru_reg_ids); i++) {
+ reg_id = rk3288_saved_cru_reg_ids[i];
+
+ rk3288_saved_cru_regs[i] =
+ readl_relaxed(rk3288_cru_base + reg_id);
+ }
+ return 0;
+}
+
+static void rk3288_clk_resume(void)
+{
+ int i, reg_id;
+
+ for (i = ARRAY_SIZE(rk3288_saved_cru_reg_ids) - 1; i >= 0; i--) {
+ reg_id = rk3288_saved_cru_reg_ids[i];
+
+ writel_relaxed(rk3288_saved_cru_regs[i] | 0xffff0000,
+ rk3288_cru_base + reg_id);
+ }
+}
+
+static struct syscore_ops rk3288_clk_syscore_ops = {
+ .suspend = rk3288_clk_suspend,
+ .resume = rk3288_clk_resume,
+};
+
+static void rk3288_clk_sleep_init(void __iomem *reg_base)
+{
+ rk3288_cru_base = reg_base;
+ register_syscore_ops(&rk3288_clk_syscore_ops);
+}
+
+#else /* CONFIG_PM_SLEEP */
+static void rk3288_clk_sleep_init(void __iomem *reg_base) {}
+#endif
+
static void __init rk3288_clk_init(struct device_node *np)
{
void __iomem *reg_base;
@@ -810,5 +872,6 @@ static void __init rk3288_clk_init(struct device_node *np)
ROCKCHIP_SOFTRST_HIWORD_MASK);
rockchip_register_restart_notifier(RK3288_GLB_SRST_FST);
+ rk3288_clk_sleep_init(reg_base);
}
CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v4 4/6] ARM: rockchip: add suspend and resume for RK3288
2014-10-21 23:17 ` Chris Zhong
@ 2014-10-21 23:25 ` Chris Zhong
-1 siblings, 0 replies; 39+ messages in thread
From: Chris Zhong @ 2014-10-21 23:25 UTC (permalink / raw
To: Heiko Stuebner
Cc: Mike Turquette, Ian Campbell, dianders, devicetree, linux-kernel,
Kumar Gala, Russell King, linux-rockchip, Rob Herring, Pawel Moll,
Chris Zhong, Mark Rutland, linux-arm-kernel, Linus Walleij,
Tony Xie
It's a basic version of suspend and resume for rockchip, it only support RK3288
now.
Signed-off-by: Tony Xie <xxx@rock-chips.com>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---
Changes in v4:
- remove grf regmap
Changes in v3:
- move the pinmux of gpio6_c6 save and restore to pinctrl-rockchip
Changes in v2:
- add the regulator calls in prepare and finish.
- add the pinmux of gpio6_c6 save and restore
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/pm.c | 307 +++++++++++++++++++++++++++++++++++++
arch/arm/mach-rockchip/pm.h | 102 ++++++++++++
arch/arm/mach-rockchip/rockchip.c | 11 +-
arch/arm/mach-rockchip/sleep.S | 87 +++++++++++
5 files changed, 506 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-rockchip/pm.c
create mode 100644 arch/arm/mach-rockchip/pm.h
create mode 100644 arch/arm/mach-rockchip/sleep.S
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index b29d8ea..5c3a9b2 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -1,4 +1,5 @@
CFLAGS_platsmp.o := -march=armv7-a
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip.o
+obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
new file mode 100644
index 0000000..c8e0091
--- /dev/null
+++ b/arch/arm/mach-rockchip/pm.c
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Tony Xie <tony.xie@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
+#include <linux/suspend.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regulator/machine.h>
+
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <asm/suspend.h>
+
+#include "pm.h"
+
+struct rockchip_pm_device_id {
+ const char *compatible;
+ const struct platform_suspend_ops *ops;
+ int (*init)(void);
+};
+
+static char bootram_save_data[SZ_4K];
+
+static void __iomem *rk3288_bootram_base;
+static phys_addr_t rk3288_bootram_phy;
+
+static struct regmap *pmu_regmap;
+static struct regmap *sgrf_regmap;
+
+static inline void rk3288_copy_data_to_sram(void)
+{
+ u32 resume_code_size = (u32)&rkpm_bootdata_cpu_code -
+ (u32)rockchip_slp_cpu_resume + 4;
+
+ /* save root sram data in ddr mem */
+ memcpy(rk3288_bootram_base, bootram_save_data, SZ_4K);
+ /* move resume code and data to bootsram */
+ memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
+ resume_code_size);
+}
+
+static inline void rk3288_restore_original_sram(void)
+{
+ memcpy(bootram_save_data, rk3288_bootram_base, SZ_4K);
+}
+
+static inline u32 rk3288_l2_config(void)
+{
+ u32 l2ctlr;
+
+ asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr));
+ return l2ctlr;
+}
+
+static void rk3288_fill_in_bootram(u32 level)
+{
+ rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8);
+ rkpm_bootdata_cpu_code = virt_to_phys(cpu_resume);
+
+ rkpm_bootdata_l2ctlr_f = 1;
+ rkpm_bootdata_l2ctlr = rk3288_l2_config();
+
+ if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) {
+ /*
+ * In this mode the SDRAM power domain will be off,
+ * so it need to be resumed,
+ * but now the sdram resume code is not ready.
+ * i have to set "rkpm_bootdata_ddr_code" 0.
+ */
+ rkpm_bootdata_ddr_code = 0;
+ } else {
+ rkpm_bootdata_ddr_code = 0;
+ }
+
+ rk3288_copy_data_to_sram();
+}
+
+static u32 rk3288_pmu_pwr_mode_con;
+static u32 rk3288_sgrf_soc_con0;
+
+static void rk3288_slp_mode_set(int level)
+{
+ u32 mode_set, mode_set1;
+
+ regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0);
+
+ regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,
+ &rk3288_pmu_pwr_mode_con);
+
+ /* set bit 8 so that system will resume to FAST_BOOT_ADDR */
+ regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
+ BIT(SGRF_FAST_BOOT_EN) | BIT(SGRF_FAST_BOOT_EN + 16));
+
+ /* booting address of resuming system is from this register value */
+ regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
+ rk3288_bootram_phy);
+
+ regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
+ PMU_ARMINT_WAKEUP_EN);
+
+ mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) |
+ BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) |
+ BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) |
+ BIT(PMU_PWR_MODE_EN) | BIT(PMU_CHIP_PD_EN) |
+ BIT(PMU_SCU_EN);
+
+ mode_set1 = BIT(PMU_CLR_CORE) | BIT(PMU_CLR_CPUP);
+
+ if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) {
+ /* arm off, logic deep sleep */
+ mode_set |= BIT(PMU_BUS_PD_EN) |
+ BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) |
+ BIT(PMU_OSC_24M_DIS) | BIT(PMU_PMU_USE_LF) |
+ BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN);
+
+ mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) |
+ BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA);
+
+ } else {
+ /*
+ * arm off, logic normal
+ * if pmu_clk_core_src_gate_en is not set,
+ * wakeup will be error
+ */
+ mode_set |= BIT(PMU_CLK_CORE_SRC_GATE_EN);
+ }
+
+ regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, mode_set);
+
+ regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON1, mode_set1);
+}
+
+static void rk3288_slp_mode_set_resume(void)
+{
+ regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON,
+ rk3288_pmu_pwr_mode_con);
+
+ regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
+ rk3288_sgrf_soc_con0 | BIT(SGRF_FAST_BOOT_EN + 16));
+}
+
+/*
+ * level: used to control the level of sleep mode.
+ * ROCKCHIP_ARM_OFF_LOGIC_NORMAL : arm is off and logic is in normal
+ * sleep mode.
+ * ROCKCHIP_ARM_OFF_LOGIC_DEEP : arm is off and logic is in deep sleep mode
+ */
+static void rk3288_save_settings(u32 level)
+{
+ rk3288_fill_in_bootram(level);
+
+ rk3288_slp_mode_set(level);
+}
+
+static void rk3288_restore_settings(void)
+{
+ rk3288_slp_mode_set_resume();
+
+ rk3288_restore_original_sram();
+}
+
+static int rockchip_lpmode_enter(unsigned long arg)
+{
+ flush_cache_all();
+
+ cpu_do_idle();
+
+ pr_info("Failed to suspend the system\n");
+
+ return 1;
+}
+
+static int rk3288_suspend_enter(suspend_state_t state)
+{
+ local_fiq_disable();
+
+ rk3288_save_settings(ROCKCHIP_ARM_OFF_LOGIC_NORMAL);
+
+ cpu_suspend(0, rockchip_lpmode_enter);
+
+ rk3288_restore_settings();
+
+ local_fiq_enable();
+
+ return 0;
+}
+
+static int rk3288_suspend_prepare(void)
+{
+ return regulator_suspend_prepare(PM_SUSPEND_MEM);
+}
+
+static void rk3288_suspend_finish(void)
+{
+ if (regulator_suspend_finish())
+ pr_warn("suspend finish failed\n");
+}
+
+static int rk3288_suspend_iomap(void)
+{
+ struct device_node *node;
+ struct resource res;
+
+ node = of_find_compatible_node(NULL, NULL, "rockchip,rk3288-pmu-sram");
+ if (!node) {
+ pr_err("%s: could not find bootram dt node\n", __func__);
+ return -1;
+ }
+
+ rk3288_bootram_base = of_iomap(node, 0);
+ if (!rk3288_bootram_base) {
+ pr_err("%s: could not map bootram base\n", __func__);
+ return -1;
+ }
+
+ if (of_address_to_resource(node, 0, &res)) {
+ pr_err("%s: could not get bootram phy addr\n", __func__);
+ return -1;
+ }
+
+ rk3288_bootram_phy = res.start;
+
+ return 0;
+}
+
+static int rk3288_suspend_init(void)
+{
+ int ret;
+
+ pmu_regmap = syscon_regmap_lookup_by_compatible(
+ "rockchip,rk3288-pmu");
+
+ if (IS_ERR(pmu_regmap)) {
+ pr_err("%s: could not find pmu regmap\n", __func__);
+ return -1;
+ }
+
+ sgrf_regmap = syscon_regmap_lookup_by_compatible(
+ "rockchip,rk3288-sgrf");
+
+ if (IS_ERR(sgrf_regmap)) {
+ pr_err("%s: could not find sgrf regmap\n", __func__);
+ return -1;
+ }
+
+ ret = rk3288_suspend_iomap();
+
+ return ret;
+}
+
+static const struct platform_suspend_ops rk3288_suspend_ops = {
+ .enter = rk3288_suspend_enter,
+ .valid = suspend_valid_only_mem,
+ .prepare = rk3288_suspend_prepare,
+ .finish = rk3288_suspend_finish,
+};
+
+static const struct rockchip_pm_device_id rockchip_pm_dt_match[] __initconst = {
+ {
+ .compatible = "rockchip,rk3288",
+ .ops = &rk3288_suspend_ops,
+ .init = rk3288_suspend_init,
+ },
+ { /* sentinel */ },
+};
+
+void __init rockchip_suspend_init(void)
+{
+ const struct rockchip_pm_device_id *matches =
+ rockchip_pm_dt_match;
+
+ while (matches->compatible && matches->ops) {
+ if (of_machine_is_compatible(matches->compatible))
+ break;
+ matches++;
+ }
+
+ if (!matches->compatible || !matches->ops) {
+ pr_err("%s:there is not a machine matched\n", __func__);
+ return;
+ }
+
+ if (matches->init) {
+ if (matches->init()) {
+ pr_err("%s: matches init error\n", __func__);
+ return;
+ }
+ }
+
+ suspend_set_ops(matches->ops);
+}
diff --git a/arch/arm/mach-rockchip/pm.h b/arch/arm/mach-rockchip/pm.h
new file mode 100644
index 0000000..8e4c359
--- /dev/null
+++ b/arch/arm/mach-rockchip/pm.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Tony Xie <tony.xie@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __MACH_ROCKCHIP_PM_H
+#define __MACH_ROCKCHIP_PM_H
+
+extern unsigned long rkpm_bootdata_cpusp;
+extern unsigned long rkpm_bootdata_cpu_code;
+extern unsigned long rkpm_bootdata_l2ctlr_f;
+extern unsigned long rkpm_bootdata_l2ctlr;
+extern unsigned long rkpm_bootdata_ddr_code;
+extern unsigned long rkpm_bootdata_ddr_data;
+/* The function selction of low power mode */
+/* arm is off and logic is in normal sleep mode */
+#define ROCKCHIP_ARM_OFF_LOGIC_NORMAL (0)
+/* arm is off and logic is in deep sleep mode */
+#define ROCKCHIP_ARM_OFF_LOGIC_DEEP (1)
+
+void rockchip_slp_cpu_resume(void);
+void __init rockchip_suspend_init(void);
+
+/****** following is rk3288 defined **********/
+#define RK3288_PMU_WAKEUP_CFG0 0x00
+#define RK3288_PMU_WAKEUP_CFG1 0x04
+#define RK3288_PMU_PWRMODE_CON 0x18
+#define RK3288_PMU_OSC_CNT 0x20
+#define RK3288_PMU_PLL_CNT 0x24
+#define RK3288_PMU_STABL_CNT 0x28
+#define RK3288_PMU_DDR0IO_PWRON_CNT 0x2c
+#define RK3288_PMU_DDR1IO_PWRON_CNT 0x30
+#define RK3288_PMU_CORE_PWRDWN_CNT 0x34
+#define RK3288_PMU_CORE_PWRUP_CNT 0x38
+#define RK3288_PMU_GPU_PWRDWN_CNT 0x3c
+#define RK3288_PMU_GPU_PWRUP_CNT 0x40
+#define RK3288_PMU_WAKEUP_RST_CLR_CNT 0x44
+#define RK3288_PMU_PWRMODE_CON1 0x90
+
+#define RK3288_SGRF_SOC_CON0 (0x0000)
+#define RK3288_SGRF_FAST_BOOT_ADDR (0x0120)
+#define SGRF_FAST_BOOT_EN (8)
+
+#define RK3288_CRU_MODE_CON (0x50)
+#define RK3288_CRU_SEL0_CON (0x60)
+#define RK3288_CRU_SEL1_CON (0x64)
+#define RK3288_CRU_SEL10_CON (0x88)
+#define RK3288_CRU_SEL33_CON (0xe4)
+#define RK3288_CRU_SEL37_CON (0xf4)
+
+/* PMU_WAKEUP_CFG1 bits */
+#define PMU_ARMINT_WAKEUP_EN BIT(0)
+
+enum rk3288_pwr_mode_con {
+ PMU_PWR_MODE_EN = 0,
+ PMU_CLK_CORE_SRC_GATE_EN,
+ PMU_GLOBAL_INT_DISABLE,
+ PMU_L2FLUSH_EN,
+ PMU_BUS_PD_EN,
+ PMU_A12_0_PD_EN,
+ PMU_SCU_EN,
+ PMU_PLL_PD_EN,
+ PMU_CHIP_PD_EN, /* POWER OFF PIN ENABLE */
+ PMU_PWROFF_COMB,
+ PMU_ALIVE_USE_LF,
+ PMU_PMU_USE_LF,
+ PMU_OSC_24M_DIS,
+ PMU_INPUT_CLAMP_EN,
+ PMU_WAKEUP_RESET_EN,
+ PMU_SREF0_ENTER_EN,
+ PMU_SREF1_ENTER_EN,
+ PMU_DDR0IO_RET_EN,
+ PMU_DDR1IO_RET_EN,
+ PMU_DDR0_GATING_EN,
+ PMU_DDR1_GATING_EN,
+ PMU_DDR0IO_RET_DE_REQ,
+ PMU_DDR1IO_RET_DE_REQ
+};
+
+enum rk3288_pwr_mode_con1 {
+ PMU_CLR_BUS = 0,
+ PMU_CLR_CORE,
+ PMU_CLR_CPUP,
+ PMU_CLR_ALIVE,
+ PMU_CLR_DMA,
+ PMU_CLR_PERI,
+ PMU_CLR_GPU,
+ PMU_CLR_VIDEO,
+ PMU_CLR_HEVC,
+ PMU_CLR_VIO,
+};
+
+#endif /* __MACH_ROCKCHIP_PM_H */
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index 8ab9e0e..db1e40d 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -23,6 +23,12 @@
#include <asm/mach/map.h>
#include <asm/hardware/cache-l2x0.h>
#include "core.h"
+#include "pm.h"
+
+static void __init rockchip_dt_init(void)
+{
+ rockchip_suspend_init();
+}
static const char * const rockchip_board_dt_compat[] = {
"rockchip,rk2928",
@@ -34,7 +40,8 @@ static const char * const rockchip_board_dt_compat[] = {
};
DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
- .l2c_aux_val = 0,
- .l2c_aux_mask = ~0,
+ .l2c_aux_val = 0,
+ .l2c_aux_mask = ~0,
+ .init_machine = rockchip_dt_init,
.dt_compat = rockchip_board_dt_compat,
MACHINE_END
diff --git a/arch/arm/mach-rockchip/sleep.S b/arch/arm/mach-rockchip/sleep.S
new file mode 100644
index 0000000..f6c2ae2
--- /dev/null
+++ b/arch/arm/mach-rockchip/sleep.S
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Tony Xie <tony.xie@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/memory.h>
+
+.data
+/*
+ * this code will be copied from
+ * ddr to sram for system resumeing.
+ * so it is ".data section".
+ */
+.align
+
+ENTRY(rockchip_slp_cpu_resume)
+ setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set svc, irqs off
+ mrc p15, 0, r1, c0, c0, 5
+ and r1, r1, #0xf
+ cmp r1, #0
+ /* olny cpu0 can continue to run, the others is halt here */
+ beq cpu0run
+secondary_loop:
+ wfe
+ b secondary_loop
+cpu0run:
+ ldr r3, rkpm_bootdata_l2ctlr_f
+ cmp r3, #0
+ beq sp_set
+ ldr r3, rkpm_bootdata_l2ctlr
+ mcr p15, 1, r3, c9, c0, 2
+sp_set:
+ ldr sp, rkpm_bootdata_cpusp
+
+ ldr r1, rkpm_bootdata_ddr_code
+ cmp r1, #0
+ beq res
+ ldr r0, rkpm_bootdata_ddr_data
+ blx r1
+res:
+ ldr r1, rkpm_bootdata_cpu_code
+ bx r1
+ENDPROC(rockchip_slp_cpu_resume)
+
+/* Parameters filled in by the kernel */
+
+/* Code to jump to for DDR resume code, or NULL */
+ .global rkpm_bootdata_ddr_code
+rkpm_bootdata_ddr_code:
+ .long 0
+
+/* Data to pass to DDR resume data */
+ .global rkpm_bootdata_ddr_data
+rkpm_bootdata_ddr_data:
+ .long 0
+
+/* Flag for whether to restore L2CTLR on resume */
+ .global rkpm_bootdata_l2ctlr_f
+rkpm_bootdata_l2ctlr_f:
+ .long 0
+
+/* Saved L2CTLR to restore on resume */
+ .global rkpm_bootdata_l2ctlr
+rkpm_bootdata_l2ctlr:
+ .long 0
+
+/* CPU resume SP addr */
+ .globl rkpm_bootdata_cpusp
+rkpm_bootdata_cpusp:
+ .long 0
+
+/* CPU resume function (physical address) */
+ .globl rkpm_bootdata_cpu_code
+rkpm_bootdata_cpu_code:
+ .long 0
--
1.7.9.5
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v4 4/6] ARM: rockchip: add suspend and resume for RK3288
@ 2014-10-21 23:25 ` Chris Zhong
0 siblings, 0 replies; 39+ messages in thread
From: Chris Zhong @ 2014-10-21 23:25 UTC (permalink / raw
To: linux-arm-kernel
It's a basic version of suspend and resume for rockchip, it only support RK3288
now.
Signed-off-by: Tony Xie <xxx@rock-chips.com>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---
Changes in v4:
- remove grf regmap
Changes in v3:
- move the pinmux of gpio6_c6 save and restore to pinctrl-rockchip
Changes in v2:
- add the regulator calls in prepare and finish.
- add the pinmux of gpio6_c6 save and restore
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/pm.c | 307 +++++++++++++++++++++++++++++++++++++
arch/arm/mach-rockchip/pm.h | 102 ++++++++++++
arch/arm/mach-rockchip/rockchip.c | 11 +-
arch/arm/mach-rockchip/sleep.S | 87 +++++++++++
5 files changed, 506 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-rockchip/pm.c
create mode 100644 arch/arm/mach-rockchip/pm.h
create mode 100644 arch/arm/mach-rockchip/sleep.S
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index b29d8ea..5c3a9b2 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -1,4 +1,5 @@
CFLAGS_platsmp.o := -march=armv7-a
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip.o
+obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
new file mode 100644
index 0000000..c8e0091
--- /dev/null
+++ b/arch/arm/mach-rockchip/pm.c
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Tony Xie <tony.xie@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
+#include <linux/suspend.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regulator/machine.h>
+
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <asm/suspend.h>
+
+#include "pm.h"
+
+struct rockchip_pm_device_id {
+ const char *compatible;
+ const struct platform_suspend_ops *ops;
+ int (*init)(void);
+};
+
+static char bootram_save_data[SZ_4K];
+
+static void __iomem *rk3288_bootram_base;
+static phys_addr_t rk3288_bootram_phy;
+
+static struct regmap *pmu_regmap;
+static struct regmap *sgrf_regmap;
+
+static inline void rk3288_copy_data_to_sram(void)
+{
+ u32 resume_code_size = (u32)&rkpm_bootdata_cpu_code -
+ (u32)rockchip_slp_cpu_resume + 4;
+
+ /* save root sram data in ddr mem */
+ memcpy(rk3288_bootram_base, bootram_save_data, SZ_4K);
+ /* move resume code and data to bootsram */
+ memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
+ resume_code_size);
+}
+
+static inline void rk3288_restore_original_sram(void)
+{
+ memcpy(bootram_save_data, rk3288_bootram_base, SZ_4K);
+}
+
+static inline u32 rk3288_l2_config(void)
+{
+ u32 l2ctlr;
+
+ asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr));
+ return l2ctlr;
+}
+
+static void rk3288_fill_in_bootram(u32 level)
+{
+ rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8);
+ rkpm_bootdata_cpu_code = virt_to_phys(cpu_resume);
+
+ rkpm_bootdata_l2ctlr_f = 1;
+ rkpm_bootdata_l2ctlr = rk3288_l2_config();
+
+ if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) {
+ /*
+ * In this mode the SDRAM power domain will be off,
+ * so it need to be resumed,
+ * but now the sdram resume code is not ready.
+ * i have to set "rkpm_bootdata_ddr_code" 0.
+ */
+ rkpm_bootdata_ddr_code = 0;
+ } else {
+ rkpm_bootdata_ddr_code = 0;
+ }
+
+ rk3288_copy_data_to_sram();
+}
+
+static u32 rk3288_pmu_pwr_mode_con;
+static u32 rk3288_sgrf_soc_con0;
+
+static void rk3288_slp_mode_set(int level)
+{
+ u32 mode_set, mode_set1;
+
+ regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0);
+
+ regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,
+ &rk3288_pmu_pwr_mode_con);
+
+ /* set bit 8 so that system will resume to FAST_BOOT_ADDR */
+ regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
+ BIT(SGRF_FAST_BOOT_EN) | BIT(SGRF_FAST_BOOT_EN + 16));
+
+ /* booting address of resuming system is from this register value */
+ regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
+ rk3288_bootram_phy);
+
+ regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
+ PMU_ARMINT_WAKEUP_EN);
+
+ mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) |
+ BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) |
+ BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) |
+ BIT(PMU_PWR_MODE_EN) | BIT(PMU_CHIP_PD_EN) |
+ BIT(PMU_SCU_EN);
+
+ mode_set1 = BIT(PMU_CLR_CORE) | BIT(PMU_CLR_CPUP);
+
+ if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) {
+ /* arm off, logic deep sleep */
+ mode_set |= BIT(PMU_BUS_PD_EN) |
+ BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) |
+ BIT(PMU_OSC_24M_DIS) | BIT(PMU_PMU_USE_LF) |
+ BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN);
+
+ mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) |
+ BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA);
+
+ } else {
+ /*
+ * arm off, logic normal
+ * if pmu_clk_core_src_gate_en is not set,
+ * wakeup will be error
+ */
+ mode_set |= BIT(PMU_CLK_CORE_SRC_GATE_EN);
+ }
+
+ regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, mode_set);
+
+ regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON1, mode_set1);
+}
+
+static void rk3288_slp_mode_set_resume(void)
+{
+ regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON,
+ rk3288_pmu_pwr_mode_con);
+
+ regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
+ rk3288_sgrf_soc_con0 | BIT(SGRF_FAST_BOOT_EN + 16));
+}
+
+/*
+ * level: used to control the level of sleep mode.
+ * ROCKCHIP_ARM_OFF_LOGIC_NORMAL : arm is off and logic is in normal
+ * sleep mode.
+ * ROCKCHIP_ARM_OFF_LOGIC_DEEP : arm is off and logic is in deep sleep mode
+ */
+static void rk3288_save_settings(u32 level)
+{
+ rk3288_fill_in_bootram(level);
+
+ rk3288_slp_mode_set(level);
+}
+
+static void rk3288_restore_settings(void)
+{
+ rk3288_slp_mode_set_resume();
+
+ rk3288_restore_original_sram();
+}
+
+static int rockchip_lpmode_enter(unsigned long arg)
+{
+ flush_cache_all();
+
+ cpu_do_idle();
+
+ pr_info("Failed to suspend the system\n");
+
+ return 1;
+}
+
+static int rk3288_suspend_enter(suspend_state_t state)
+{
+ local_fiq_disable();
+
+ rk3288_save_settings(ROCKCHIP_ARM_OFF_LOGIC_NORMAL);
+
+ cpu_suspend(0, rockchip_lpmode_enter);
+
+ rk3288_restore_settings();
+
+ local_fiq_enable();
+
+ return 0;
+}
+
+static int rk3288_suspend_prepare(void)
+{
+ return regulator_suspend_prepare(PM_SUSPEND_MEM);
+}
+
+static void rk3288_suspend_finish(void)
+{
+ if (regulator_suspend_finish())
+ pr_warn("suspend finish failed\n");
+}
+
+static int rk3288_suspend_iomap(void)
+{
+ struct device_node *node;
+ struct resource res;
+
+ node = of_find_compatible_node(NULL, NULL, "rockchip,rk3288-pmu-sram");
+ if (!node) {
+ pr_err("%s: could not find bootram dt node\n", __func__);
+ return -1;
+ }
+
+ rk3288_bootram_base = of_iomap(node, 0);
+ if (!rk3288_bootram_base) {
+ pr_err("%s: could not map bootram base\n", __func__);
+ return -1;
+ }
+
+ if (of_address_to_resource(node, 0, &res)) {
+ pr_err("%s: could not get bootram phy addr\n", __func__);
+ return -1;
+ }
+
+ rk3288_bootram_phy = res.start;
+
+ return 0;
+}
+
+static int rk3288_suspend_init(void)
+{
+ int ret;
+
+ pmu_regmap = syscon_regmap_lookup_by_compatible(
+ "rockchip,rk3288-pmu");
+
+ if (IS_ERR(pmu_regmap)) {
+ pr_err("%s: could not find pmu regmap\n", __func__);
+ return -1;
+ }
+
+ sgrf_regmap = syscon_regmap_lookup_by_compatible(
+ "rockchip,rk3288-sgrf");
+
+ if (IS_ERR(sgrf_regmap)) {
+ pr_err("%s: could not find sgrf regmap\n", __func__);
+ return -1;
+ }
+
+ ret = rk3288_suspend_iomap();
+
+ return ret;
+}
+
+static const struct platform_suspend_ops rk3288_suspend_ops = {
+ .enter = rk3288_suspend_enter,
+ .valid = suspend_valid_only_mem,
+ .prepare = rk3288_suspend_prepare,
+ .finish = rk3288_suspend_finish,
+};
+
+static const struct rockchip_pm_device_id rockchip_pm_dt_match[] __initconst = {
+ {
+ .compatible = "rockchip,rk3288",
+ .ops = &rk3288_suspend_ops,
+ .init = rk3288_suspend_init,
+ },
+ { /* sentinel */ },
+};
+
+void __init rockchip_suspend_init(void)
+{
+ const struct rockchip_pm_device_id *matches =
+ rockchip_pm_dt_match;
+
+ while (matches->compatible && matches->ops) {
+ if (of_machine_is_compatible(matches->compatible))
+ break;
+ matches++;
+ }
+
+ if (!matches->compatible || !matches->ops) {
+ pr_err("%s:there is not a machine matched\n", __func__);
+ return;
+ }
+
+ if (matches->init) {
+ if (matches->init()) {
+ pr_err("%s: matches init error\n", __func__);
+ return;
+ }
+ }
+
+ suspend_set_ops(matches->ops);
+}
diff --git a/arch/arm/mach-rockchip/pm.h b/arch/arm/mach-rockchip/pm.h
new file mode 100644
index 0000000..8e4c359
--- /dev/null
+++ b/arch/arm/mach-rockchip/pm.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Tony Xie <tony.xie@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __MACH_ROCKCHIP_PM_H
+#define __MACH_ROCKCHIP_PM_H
+
+extern unsigned long rkpm_bootdata_cpusp;
+extern unsigned long rkpm_bootdata_cpu_code;
+extern unsigned long rkpm_bootdata_l2ctlr_f;
+extern unsigned long rkpm_bootdata_l2ctlr;
+extern unsigned long rkpm_bootdata_ddr_code;
+extern unsigned long rkpm_bootdata_ddr_data;
+/* The function selction of low power mode */
+/* arm is off and logic is in normal sleep mode */
+#define ROCKCHIP_ARM_OFF_LOGIC_NORMAL (0)
+/* arm is off and logic is in deep sleep mode */
+#define ROCKCHIP_ARM_OFF_LOGIC_DEEP (1)
+
+void rockchip_slp_cpu_resume(void);
+void __init rockchip_suspend_init(void);
+
+/****** following is rk3288 defined **********/
+#define RK3288_PMU_WAKEUP_CFG0 0x00
+#define RK3288_PMU_WAKEUP_CFG1 0x04
+#define RK3288_PMU_PWRMODE_CON 0x18
+#define RK3288_PMU_OSC_CNT 0x20
+#define RK3288_PMU_PLL_CNT 0x24
+#define RK3288_PMU_STABL_CNT 0x28
+#define RK3288_PMU_DDR0IO_PWRON_CNT 0x2c
+#define RK3288_PMU_DDR1IO_PWRON_CNT 0x30
+#define RK3288_PMU_CORE_PWRDWN_CNT 0x34
+#define RK3288_PMU_CORE_PWRUP_CNT 0x38
+#define RK3288_PMU_GPU_PWRDWN_CNT 0x3c
+#define RK3288_PMU_GPU_PWRUP_CNT 0x40
+#define RK3288_PMU_WAKEUP_RST_CLR_CNT 0x44
+#define RK3288_PMU_PWRMODE_CON1 0x90
+
+#define RK3288_SGRF_SOC_CON0 (0x0000)
+#define RK3288_SGRF_FAST_BOOT_ADDR (0x0120)
+#define SGRF_FAST_BOOT_EN (8)
+
+#define RK3288_CRU_MODE_CON (0x50)
+#define RK3288_CRU_SEL0_CON (0x60)
+#define RK3288_CRU_SEL1_CON (0x64)
+#define RK3288_CRU_SEL10_CON (0x88)
+#define RK3288_CRU_SEL33_CON (0xe4)
+#define RK3288_CRU_SEL37_CON (0xf4)
+
+/* PMU_WAKEUP_CFG1 bits */
+#define PMU_ARMINT_WAKEUP_EN BIT(0)
+
+enum rk3288_pwr_mode_con {
+ PMU_PWR_MODE_EN = 0,
+ PMU_CLK_CORE_SRC_GATE_EN,
+ PMU_GLOBAL_INT_DISABLE,
+ PMU_L2FLUSH_EN,
+ PMU_BUS_PD_EN,
+ PMU_A12_0_PD_EN,
+ PMU_SCU_EN,
+ PMU_PLL_PD_EN,
+ PMU_CHIP_PD_EN, /* POWER OFF PIN ENABLE */
+ PMU_PWROFF_COMB,
+ PMU_ALIVE_USE_LF,
+ PMU_PMU_USE_LF,
+ PMU_OSC_24M_DIS,
+ PMU_INPUT_CLAMP_EN,
+ PMU_WAKEUP_RESET_EN,
+ PMU_SREF0_ENTER_EN,
+ PMU_SREF1_ENTER_EN,
+ PMU_DDR0IO_RET_EN,
+ PMU_DDR1IO_RET_EN,
+ PMU_DDR0_GATING_EN,
+ PMU_DDR1_GATING_EN,
+ PMU_DDR0IO_RET_DE_REQ,
+ PMU_DDR1IO_RET_DE_REQ
+};
+
+enum rk3288_pwr_mode_con1 {
+ PMU_CLR_BUS = 0,
+ PMU_CLR_CORE,
+ PMU_CLR_CPUP,
+ PMU_CLR_ALIVE,
+ PMU_CLR_DMA,
+ PMU_CLR_PERI,
+ PMU_CLR_GPU,
+ PMU_CLR_VIDEO,
+ PMU_CLR_HEVC,
+ PMU_CLR_VIO,
+};
+
+#endif /* __MACH_ROCKCHIP_PM_H */
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index 8ab9e0e..db1e40d 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -23,6 +23,12 @@
#include <asm/mach/map.h>
#include <asm/hardware/cache-l2x0.h>
#include "core.h"
+#include "pm.h"
+
+static void __init rockchip_dt_init(void)
+{
+ rockchip_suspend_init();
+}
static const char * const rockchip_board_dt_compat[] = {
"rockchip,rk2928",
@@ -34,7 +40,8 @@ static const char * const rockchip_board_dt_compat[] = {
};
DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
- .l2c_aux_val = 0,
- .l2c_aux_mask = ~0,
+ .l2c_aux_val = 0,
+ .l2c_aux_mask = ~0,
+ .init_machine = rockchip_dt_init,
.dt_compat = rockchip_board_dt_compat,
MACHINE_END
diff --git a/arch/arm/mach-rockchip/sleep.S b/arch/arm/mach-rockchip/sleep.S
new file mode 100644
index 0000000..f6c2ae2
--- /dev/null
+++ b/arch/arm/mach-rockchip/sleep.S
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Tony Xie <tony.xie@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/memory.h>
+
+.data
+/*
+ * this code will be copied from
+ * ddr to sram for system resumeing.
+ * so it is ".data section".
+ */
+.align
+
+ENTRY(rockchip_slp_cpu_resume)
+ setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set svc, irqs off
+ mrc p15, 0, r1, c0, c0, 5
+ and r1, r1, #0xf
+ cmp r1, #0
+ /* olny cpu0 can continue to run, the others is halt here */
+ beq cpu0run
+secondary_loop:
+ wfe
+ b secondary_loop
+cpu0run:
+ ldr r3, rkpm_bootdata_l2ctlr_f
+ cmp r3, #0
+ beq sp_set
+ ldr r3, rkpm_bootdata_l2ctlr
+ mcr p15, 1, r3, c9, c0, 2
+sp_set:
+ ldr sp, rkpm_bootdata_cpusp
+
+ ldr r1, rkpm_bootdata_ddr_code
+ cmp r1, #0
+ beq res
+ ldr r0, rkpm_bootdata_ddr_data
+ blx r1
+res:
+ ldr r1, rkpm_bootdata_cpu_code
+ bx r1
+ENDPROC(rockchip_slp_cpu_resume)
+
+/* Parameters filled in by the kernel */
+
+/* Code to jump to for DDR resume code, or NULL */
+ .global rkpm_bootdata_ddr_code
+rkpm_bootdata_ddr_code:
+ .long 0
+
+/* Data to pass to DDR resume data */
+ .global rkpm_bootdata_ddr_data
+rkpm_bootdata_ddr_data:
+ .long 0
+
+/* Flag for whether to restore L2CTLR on resume */
+ .global rkpm_bootdata_l2ctlr_f
+rkpm_bootdata_l2ctlr_f:
+ .long 0
+
+/* Saved L2CTLR to restore on resume */
+ .global rkpm_bootdata_l2ctlr
+rkpm_bootdata_l2ctlr:
+ .long 0
+
+/* CPU resume SP addr */
+ .globl rkpm_bootdata_cpusp
+rkpm_bootdata_cpusp:
+ .long 0
+
+/* CPU resume function (physical address) */
+ .globl rkpm_bootdata_cpu_code
+rkpm_bootdata_cpu_code:
+ .long 0
--
1.7.9.5
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v4 5/6] ARM: rockchip: Add pmu-sram binding
@ 2014-10-21 23:26 ` Chris Zhong
0 siblings, 0 replies; 39+ messages in thread
From: Chris Zhong @ 2014-10-21 23:26 UTC (permalink / raw
To: Heiko Stuebner
Cc: Mike Turquette, Ian Campbell, dianders, devicetree, linux-kernel,
Kumar Gala, Russell King, linux-rockchip, Rob Herring, Pawel Moll,
Chris Zhong, Mark Rutland, linux-arm-kernel, Linus Walleij,
Tony Xie
The pmu-sram is used to store resume code, suspend/resume need get the
address of it. Therefore add a binding and documentation for it.
Signed-off-by: Tony Xie <xxx@rock-chips.com>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
.../devicetree/bindings/arm/rockchip/pmu-sram.txt | 15 +++++++++++++++
1 file changed, 15 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt b/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
new file mode 100644
index 0000000..77284c0
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
@@ -0,0 +1,15 @@
+Rockchip SRAM for pmu:
+------------------------------
+
+The sram of pmu is used to store the function of resume from maskrom(the 1st
+level loader).
+
+Required node properties:
+- compatible : should be "rockchip,rk3288-pmu-sram"
+- reg : physical base address and the size of the registers window
+
+Example:
+ pmu_intmem@ff720000 {
+ compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
+ reg = <0xff720000 0x4000>;
+ };
--
1.7.9.5
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v4 5/6] ARM: rockchip: Add pmu-sram binding
@ 2014-10-21 23:26 ` Chris Zhong
0 siblings, 0 replies; 39+ messages in thread
From: Chris Zhong @ 2014-10-21 23:26 UTC (permalink / raw
To: Heiko Stuebner
Cc: Mike Turquette, Ian Campbell, dianders-F7+t8E8rja9g9hUCZPvPmw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Kumar Gala, Russell King,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring,
Pawel Moll, Chris Zhong, Mark Rutland,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Linus Walleij,
Tony Xie
The pmu-sram is used to store resume code, suspend/resume need get the
address of it. Therefore add a binding and documentation for it.
Signed-off-by: Tony Xie <xxx-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
.../devicetree/bindings/arm/rockchip/pmu-sram.txt | 15 +++++++++++++++
1 file changed, 15 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt b/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
new file mode 100644
index 0000000..77284c0
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
@@ -0,0 +1,15 @@
+Rockchip SRAM for pmu:
+------------------------------
+
+The sram of pmu is used to store the function of resume from maskrom(the 1st
+level loader).
+
+Required node properties:
+- compatible : should be "rockchip,rk3288-pmu-sram"
+- reg : physical base address and the size of the registers window
+
+Example:
+ pmu_intmem@ff720000 {
+ compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
+ reg = <0xff720000 0x4000>;
+ };
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v4 5/6] ARM: rockchip: Add pmu-sram binding
@ 2014-10-21 23:26 ` Chris Zhong
0 siblings, 0 replies; 39+ messages in thread
From: Chris Zhong @ 2014-10-21 23:26 UTC (permalink / raw
To: linux-arm-kernel
The pmu-sram is used to store resume code, suspend/resume need get the
address of it. Therefore add a binding and documentation for it.
Signed-off-by: Tony Xie <xxx@rock-chips.com>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
.../devicetree/bindings/arm/rockchip/pmu-sram.txt | 15 +++++++++++++++
1 file changed, 15 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt b/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
new file mode 100644
index 0000000..77284c0
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
@@ -0,0 +1,15 @@
+Rockchip SRAM for pmu:
+------------------------------
+
+The sram of pmu is used to store the function of resume from maskrom(the 1st
+level loader).
+
+Required node properties:
+- compatible : should be "rockchip,rk3288-pmu-sram"
+- reg : physical base address and the size of the registers window
+
+Example:
+ pmu_intmem at ff720000 {
+ compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
+ reg = <0xff720000 0x4000>;
+ };
--
1.7.9.5
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v4 6/6] ARM: dts: add RK3288 suspend support
@ 2014-10-21 23:26 ` Chris Zhong
0 siblings, 0 replies; 39+ messages in thread
From: Chris Zhong @ 2014-10-21 23:26 UTC (permalink / raw
To: Heiko Stuebner
Cc: Mike Turquette, Ian Campbell, dianders, devicetree, linux-kernel,
Kumar Gala, Russell King, linux-rockchip, Rob Herring, Pawel Moll,
Chris Zhong, Mark Rutland, linux-arm-kernel, Linus Walleij,
Tony Xie
add pmu_intmem node for suspend, add global_pwroff pinctrl.
The pmu_intmem is used to store the resume code.
global_pwroff is held low level at work, it would be pull to high
when entering suspend. PMICs can get this signal, then shut down
some power rails. So please reference the global_pwroff pinctrl
as part of the PMIC config.
Signed-off-by: Tony Xie <xxx@rock-chips.com>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- put "rockchip,rk3288-pmu-sram" to first
arch/arm/boot/dts/rk3288.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 874e66d..c52fe09 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -439,6 +439,11 @@
status = "disabled";
};
+ pmu_intmem@ff720000 {
+ compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
+ reg = <0xff720000 0x4000>;
+ };
+
pmu: power-management@ff730000 {
compatible = "rockchip,rk3288-pmu", "syscon";
reg = <0xff730000 0x100>;
@@ -634,6 +639,12 @@
bias-disable;
};
+ sleep {
+ global_pwroff: global-pwroff {
+ rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v4 6/6] ARM: dts: add RK3288 suspend support
@ 2014-10-21 23:26 ` Chris Zhong
0 siblings, 0 replies; 39+ messages in thread
From: Chris Zhong @ 2014-10-21 23:26 UTC (permalink / raw
To: Heiko Stuebner
Cc: Mike Turquette, Ian Campbell, dianders-F7+t8E8rja9g9hUCZPvPmw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Kumar Gala, Russell King,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring,
Pawel Moll, Chris Zhong, Mark Rutland,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Linus Walleij,
Tony Xie
add pmu_intmem node for suspend, add global_pwroff pinctrl.
The pmu_intmem is used to store the resume code.
global_pwroff is held low level at work, it would be pull to high
when entering suspend. PMICs can get this signal, then shut down
some power rails. So please reference the global_pwroff pinctrl
as part of the PMIC config.
Signed-off-by: Tony Xie <xxx-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- put "rockchip,rk3288-pmu-sram" to first
arch/arm/boot/dts/rk3288.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 874e66d..c52fe09 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -439,6 +439,11 @@
status = "disabled";
};
+ pmu_intmem@ff720000 {
+ compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
+ reg = <0xff720000 0x4000>;
+ };
+
pmu: power-management@ff730000 {
compatible = "rockchip,rk3288-pmu", "syscon";
reg = <0xff730000 0x100>;
@@ -634,6 +639,12 @@
bias-disable;
};
+ sleep {
+ global_pwroff: global-pwroff {
+ rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v4 6/6] ARM: dts: add RK3288 suspend support
@ 2014-10-21 23:26 ` Chris Zhong
0 siblings, 0 replies; 39+ messages in thread
From: Chris Zhong @ 2014-10-21 23:26 UTC (permalink / raw
To: linux-arm-kernel
add pmu_intmem node for suspend, add global_pwroff pinctrl.
The pmu_intmem is used to store the resume code.
global_pwroff is held low level at work, it would be pull to high
when entering suspend. PMICs can get this signal, then shut down
some power rails. So please reference the global_pwroff pinctrl
as part of the PMIC config.
Signed-off-by: Tony Xie <xxx@rock-chips.com>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- put "rockchip,rk3288-pmu-sram" to first
arch/arm/boot/dts/rk3288.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 874e66d..c52fe09 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -439,6 +439,11 @@
status = "disabled";
};
+ pmu_intmem at ff720000 {
+ compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
+ reg = <0xff720000 0x4000>;
+ };
+
pmu: power-management at ff730000 {
compatible = "rockchip,rk3288-pmu", "syscon";
reg = <0xff730000 0x100>;
@@ -634,6 +639,12 @@
bias-disable;
};
+ sleep {
+ global_pwroff: global-pwroff {
+ rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH v4 1/6] pinctrl: rockchip: add suspend/resume functions
2014-10-21 23:19 ` Chris Zhong
@ 2014-10-22 4:19 ` Doug Anderson
-1 siblings, 0 replies; 39+ messages in thread
From: Doug Anderson @ 2014-10-22 4:19 UTC (permalink / raw
To: Chris Zhong
Cc: Heiko Stuebner, Mike Turquette, Ian Campbell,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Kumar Gala, Russell King, linux-rockchip, Rob Herring, Pawel Moll,
Mark Rutland, linux-arm-kernel@lists.infradead.org, Linus Walleij
Chris,
On Tue, Oct 21, 2014 at 4:19 PM, Chris Zhong <zyw@rock-chips.com> wrote:
> From: Chris <zyw@rock-chips.com>
I think your git is misconfigured. The above "From" line will make
the author end up without your last name. Heiko mentioned this in v4.
> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
> index 016f457..c4a988d 100644
> --- a/drivers/pinctrl/pinctrl-rockchip.c
> +++ b/drivers/pinctrl/pinctrl-rockchip.c
> @@ -1770,6 +1770,25 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
> return ctrl;
> }
>
> +#ifdef CONFIG_PM_SLEEP
> +static int rockchip_pinctrl_suspend(struct device *dev)
Why didn't you take Dmitry's suggestion from v3? I think you can get
rid of the #ifdef and add the "__maybe_unused" annotation to avoid
errors when PM_SLEEP isn't defined.
This does work, though, so:
Tested-by: Doug Anderson <dianders@chromium.org>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v4 1/6] pinctrl: rockchip: add suspend/resume functions
@ 2014-10-22 4:19 ` Doug Anderson
0 siblings, 0 replies; 39+ messages in thread
From: Doug Anderson @ 2014-10-22 4:19 UTC (permalink / raw
To: linux-arm-kernel
Chris,
On Tue, Oct 21, 2014 at 4:19 PM, Chris Zhong <zyw@rock-chips.com> wrote:
> From: Chris <zyw@rock-chips.com>
I think your git is misconfigured. The above "From" line will make
the author end up without your last name. Heiko mentioned this in v4.
> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
> index 016f457..c4a988d 100644
> --- a/drivers/pinctrl/pinctrl-rockchip.c
> +++ b/drivers/pinctrl/pinctrl-rockchip.c
> @@ -1770,6 +1770,25 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
> return ctrl;
> }
>
> +#ifdef CONFIG_PM_SLEEP
> +static int rockchip_pinctrl_suspend(struct device *dev)
Why didn't you take Dmitry's suggestion from v3? I think you can get
rid of the #ifdef and add the "__maybe_unused" annotation to avoid
errors when PM_SLEEP isn't defined.
This does work, though, so:
Tested-by: Doug Anderson <dianders@chromium.org>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v4 2/6] pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume
@ 2014-10-22 4:33 ` Doug Anderson
0 siblings, 0 replies; 39+ messages in thread
From: Doug Anderson @ 2014-10-22 4:33 UTC (permalink / raw
To: Chris Zhong
Cc: Heiko Stuebner, Mike Turquette, Ian Campbell,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Kumar Gala, Russell King, linux-rockchip, Rob Herring, Pawel Moll,
Mark Rutland, linux-arm-kernel@lists.infradead.org, Linus Walleij
Chris,
On Tue, Oct 21, 2014 at 4:19 PM, Chris Zhong <zyw@rock-chips.com> wrote:
> +static u32 rk3288_grf_gpio6c_iomux;
Somehow my instinct says that this should be in the "info" structure,
but I can't say exactly why (since by definition there can be only one
gpio6_c6). ...no need to change this in my opinion.
> static int rockchip_pinctrl_suspend(struct device *dev)
> {
> struct rockchip_pinctrl *info = dev_get_drvdata(dev);
> + int ret = pinctrl_force_sleep(info->pctl_dev);
> +
> + if (ret)
> + return ret;
> +
> + /*
> + * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
> + * the setting here, and restore it at resume.
> + */
> + if (info->ctrl->type == RK3288) {
> + ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
> + &rk3288_grf_gpio6c_iomux);
> + if (ret)
> + return ret;
I seriously doubt it matters, but as a nit it seems like you should
call pinctrl_force_default() in the error case (to undo
pinctrl_force_sleep).
Everything is just nits and this works for me, so:
Tested-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v4 2/6] pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume
@ 2014-10-22 4:33 ` Doug Anderson
0 siblings, 0 replies; 39+ messages in thread
From: Doug Anderson @ 2014-10-22 4:33 UTC (permalink / raw
To: Chris Zhong
Cc: Heiko Stuebner, Mike Turquette, Ian Campbell,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Kumar Gala,
Russell King, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Rob Herring, Pawel Moll, Mark Rutland,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Linus Walleij
Chris,
On Tue, Oct 21, 2014 at 4:19 PM, Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
> +static u32 rk3288_grf_gpio6c_iomux;
Somehow my instinct says that this should be in the "info" structure,
but I can't say exactly why (since by definition there can be only one
gpio6_c6). ...no need to change this in my opinion.
> static int rockchip_pinctrl_suspend(struct device *dev)
> {
> struct rockchip_pinctrl *info = dev_get_drvdata(dev);
> + int ret = pinctrl_force_sleep(info->pctl_dev);
> +
> + if (ret)
> + return ret;
> +
> + /*
> + * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
> + * the setting here, and restore it at resume.
> + */
> + if (info->ctrl->type == RK3288) {
> + ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
> + &rk3288_grf_gpio6c_iomux);
> + if (ret)
> + return ret;
I seriously doubt it matters, but as a nit it seems like you should
call pinctrl_force_default() in the error case (to undo
pinctrl_force_sleep).
Everything is just nits and this works for me, so:
Tested-by: Doug Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Reviewed-by: Doug Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v4 2/6] pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume
@ 2014-10-22 4:33 ` Doug Anderson
0 siblings, 0 replies; 39+ messages in thread
From: Doug Anderson @ 2014-10-22 4:33 UTC (permalink / raw
To: linux-arm-kernel
Chris,
On Tue, Oct 21, 2014 at 4:19 PM, Chris Zhong <zyw@rock-chips.com> wrote:
> +static u32 rk3288_grf_gpio6c_iomux;
Somehow my instinct says that this should be in the "info" structure,
but I can't say exactly why (since by definition there can be only one
gpio6_c6). ...no need to change this in my opinion.
> static int rockchip_pinctrl_suspend(struct device *dev)
> {
> struct rockchip_pinctrl *info = dev_get_drvdata(dev);
> + int ret = pinctrl_force_sleep(info->pctl_dev);
> +
> + if (ret)
> + return ret;
> +
> + /*
> + * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
> + * the setting here, and restore it at resume.
> + */
> + if (info->ctrl->type == RK3288) {
> + ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
> + &rk3288_grf_gpio6c_iomux);
> + if (ret)
> + return ret;
I seriously doubt it matters, but as a nit it seems like you should
call pinctrl_force_default() in the error case (to undo
pinctrl_force_sleep).
Everything is just nits and this works for me, so:
Tested-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v4 3/6] clk: rockchip: RK3288: add suspend and resume
@ 2014-10-22 4:58 ` Doug Anderson
0 siblings, 0 replies; 39+ messages in thread
From: Doug Anderson @ 2014-10-22 4:58 UTC (permalink / raw
To: Chris Zhong
Cc: Heiko Stuebner, Mike Turquette, Ian Campbell,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Kumar Gala, Russell King, linux-rockchip, Rob Herring, Pawel Moll,
Mark Rutland, linux-arm-kernel@lists.infradead.org, Linus Walleij,
Tony Xie
Chris,
On Tue, Oct 21, 2014 at 4:25 PM, Chris Zhong <zyw@rock-chips.com> wrote:
> +#ifdef CONFIG_PM_SLEEP
> +static void __iomem *rk3288_cru_base;
> +static const int rk3288_saved_cru_reg_ids[] = {
> + RK3288_MODE_CON,
> + RK3288_CLKSEL_CON(0),
> + RK3288_CLKSEL_CON(1),
> + RK3288_CLKSEL_CON(10),
> + RK3288_CLKSEL_CON(33),
> + RK3288_CLKSEL_CON(37),
I'm still not 100% certain why these registers were picked. Are they
all needed? Are we sure that no extras are needed?
I'll try to find some time to research, but if you happen to know the
answer that'd be nice.
> +};
> +
> +static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)];
> +
> +/*
> + * cru will be set in maskrom when system wake up from fastboot
> + * mode in suspend,
> + * so the operation is saving the changed regs.
> + * The apll/cpll/gpll will be set into slow mode in maskrom.
> + * It is mean that resume code run in 24m quit slowly!
s/quit/quite
> + * so we must resume these plls as soon as possible.
This function doesn't actually resume PLLs, it just restores dividers / etc.
I will say that with this patch the "clk_summary" doesn't change
before and after suspend/resume. Without this patch I see this diff
before/after:
< l2ram 0 0 600000000
0 0
< aclk_core_m0 0 0 600000000
0 0
< aclk_core_mp 0 0 360000000
0 0
< atclk 0 0 360000000
0 0
< pclk_dbg_pre 0 0 360000000
0 0
< pclk_core_niu 0 0
360000000 0 0
< cs_dbg 0 0 360000000
0 0
< pclk_dbg 0 0 360000000
0 0
---
> l2ram 0 0 1800000000 0 0
> aclk_core_m0 0 0 1800000000 0 0
> aclk_core_mp 0 0 1800000000 0 0
> atclk 0 0 1800000000 0 0
> pclk_dbg_pre 0 0 1800000000 0 0
> pclk_core_niu 0 0 1800000000 0 0
> cs_dbg 0 0 1800000000 0 0
> pclk_dbg 0 0 1800000000 0 0
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v4 3/6] clk: rockchip: RK3288: add suspend and resume
@ 2014-10-22 4:58 ` Doug Anderson
0 siblings, 0 replies; 39+ messages in thread
From: Doug Anderson @ 2014-10-22 4:58 UTC (permalink / raw
To: Chris Zhong
Cc: Heiko Stuebner, Mike Turquette, Ian Campbell,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Kumar Gala,
Russell King, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Rob Herring, Pawel Moll, Mark Rutland,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Linus Walleij, Tony Xie
Chris,
On Tue, Oct 21, 2014 at 4:25 PM, Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
> +#ifdef CONFIG_PM_SLEEP
> +static void __iomem *rk3288_cru_base;
> +static const int rk3288_saved_cru_reg_ids[] = {
> + RK3288_MODE_CON,
> + RK3288_CLKSEL_CON(0),
> + RK3288_CLKSEL_CON(1),
> + RK3288_CLKSEL_CON(10),
> + RK3288_CLKSEL_CON(33),
> + RK3288_CLKSEL_CON(37),
I'm still not 100% certain why these registers were picked. Are they
all needed? Are we sure that no extras are needed?
I'll try to find some time to research, but if you happen to know the
answer that'd be nice.
> +};
> +
> +static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)];
> +
> +/*
> + * cru will be set in maskrom when system wake up from fastboot
> + * mode in suspend,
> + * so the operation is saving the changed regs.
> + * The apll/cpll/gpll will be set into slow mode in maskrom.
> + * It is mean that resume code run in 24m quit slowly!
s/quit/quite
> + * so we must resume these plls as soon as possible.
This function doesn't actually resume PLLs, it just restores dividers / etc.
I will say that with this patch the "clk_summary" doesn't change
before and after suspend/resume. Without this patch I see this diff
before/after:
< l2ram 0 0 600000000
0 0
< aclk_core_m0 0 0 600000000
0 0
< aclk_core_mp 0 0 360000000
0 0
< atclk 0 0 360000000
0 0
< pclk_dbg_pre 0 0 360000000
0 0
< pclk_core_niu 0 0
360000000 0 0
< cs_dbg 0 0 360000000
0 0
< pclk_dbg 0 0 360000000
0 0
---
> l2ram 0 0 1800000000 0 0
> aclk_core_m0 0 0 1800000000 0 0
> aclk_core_mp 0 0 1800000000 0 0
> atclk 0 0 1800000000 0 0
> pclk_dbg_pre 0 0 1800000000 0 0
> pclk_core_niu 0 0 1800000000 0 0
> cs_dbg 0 0 1800000000 0 0
> pclk_dbg 0 0 1800000000 0 0
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v4 3/6] clk: rockchip: RK3288: add suspend and resume
@ 2014-10-22 4:58 ` Doug Anderson
0 siblings, 0 replies; 39+ messages in thread
From: Doug Anderson @ 2014-10-22 4:58 UTC (permalink / raw
To: linux-arm-kernel
Chris,
On Tue, Oct 21, 2014 at 4:25 PM, Chris Zhong <zyw@rock-chips.com> wrote:
> +#ifdef CONFIG_PM_SLEEP
> +static void __iomem *rk3288_cru_base;
> +static const int rk3288_saved_cru_reg_ids[] = {
> + RK3288_MODE_CON,
> + RK3288_CLKSEL_CON(0),
> + RK3288_CLKSEL_CON(1),
> + RK3288_CLKSEL_CON(10),
> + RK3288_CLKSEL_CON(33),
> + RK3288_CLKSEL_CON(37),
I'm still not 100% certain why these registers were picked. Are they
all needed? Are we sure that no extras are needed?
I'll try to find some time to research, but if you happen to know the
answer that'd be nice.
> +};
> +
> +static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)];
> +
> +/*
> + * cru will be set in maskrom when system wake up from fastboot
> + * mode in suspend,
> + * so the operation is saving the changed regs.
> + * The apll/cpll/gpll will be set into slow mode in maskrom.
> + * It is mean that resume code run in 24m quit slowly!
s/quit/quite
> + * so we must resume these plls as soon as possible.
This function doesn't actually resume PLLs, it just restores dividers / etc.
I will say that with this patch the "clk_summary" doesn't change
before and after suspend/resume. Without this patch I see this diff
before/after:
< l2ram 0 0 600000000
0 0
< aclk_core_m0 0 0 600000000
0 0
< aclk_core_mp 0 0 360000000
0 0
< atclk 0 0 360000000
0 0
< pclk_dbg_pre 0 0 360000000
0 0
< pclk_core_niu 0 0
360000000 0 0
< cs_dbg 0 0 360000000
0 0
< pclk_dbg 0 0 360000000
0 0
---
> l2ram 0 0 1800000000 0 0
> aclk_core_m0 0 0 1800000000 0 0
> aclk_core_mp 0 0 1800000000 0 0
> atclk 0 0 1800000000 0 0
> pclk_dbg_pre 0 0 1800000000 0 0
> pclk_core_niu 0 0 1800000000 0 0
> cs_dbg 0 0 1800000000 0 0
> pclk_dbg 0 0 1800000000 0 0
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v4 4/6] ARM: rockchip: add suspend and resume for RK3288
2014-10-21 23:25 ` Chris Zhong
@ 2014-10-22 5:01 ` Doug Anderson
-1 siblings, 0 replies; 39+ messages in thread
From: Doug Anderson @ 2014-10-22 5:01 UTC (permalink / raw
To: Chris Zhong
Cc: Heiko Stuebner, Mike Turquette, Ian Campbell,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Kumar Gala, Russell King, linux-rockchip, Rob Herring, Pawel Moll,
Mark Rutland, linux-arm-kernel@lists.infradead.org, Linus Walleij,
Tony Xie
Chris,
On Tue, Oct 21, 2014 at 4:25 PM, Chris Zhong <zyw@rock-chips.com> wrote:
> @@ -34,7 +40,8 @@ static const char * const rockchip_board_dt_compat[] = {
> };
>
> DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
> - .l2c_aux_val = 0,
> - .l2c_aux_mask = ~0,
> + .l2c_aux_val = 0,
> + .l2c_aux_mask = ~0,
Please avoid unrelated spacing changes.
Other than that this is looking like a good starting point. I'm sure
we'll find other things to do, but I'd be in favor of landing this and
spinning. I can see a device suspend/resume with this patch, so:
Tested-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v4 4/6] ARM: rockchip: add suspend and resume for RK3288
@ 2014-10-22 5:01 ` Doug Anderson
0 siblings, 0 replies; 39+ messages in thread
From: Doug Anderson @ 2014-10-22 5:01 UTC (permalink / raw
To: linux-arm-kernel
Chris,
On Tue, Oct 21, 2014 at 4:25 PM, Chris Zhong <zyw@rock-chips.com> wrote:
> @@ -34,7 +40,8 @@ static const char * const rockchip_board_dt_compat[] = {
> };
>
> DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
> - .l2c_aux_val = 0,
> - .l2c_aux_mask = ~0,
> + .l2c_aux_val = 0,
> + .l2c_aux_mask = ~0,
Please avoid unrelated spacing changes.
Other than that this is looking like a good starting point. I'm sure
we'll find other things to do, but I'd be in favor of landing this and
spinning. I can see a device suspend/resume with this patch, so:
Tested-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v4 6/6] ARM: dts: add RK3288 suspend support
2014-10-21 23:26 ` Chris Zhong
@ 2014-10-23 0:04 ` Doug Anderson
-1 siblings, 0 replies; 39+ messages in thread
From: Doug Anderson @ 2014-10-23 0:04 UTC (permalink / raw
To: Chris Zhong
Cc: Heiko Stuebner, Mike Turquette, Ian Campbell,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Kumar Gala, Russell King, linux-rockchip, Rob Herring, Pawel Moll,
Mark Rutland, linux-arm-kernel@lists.infradead.org, Linus Walleij,
Tony Xie
Chris,
On Tue, Oct 21, 2014 at 4:26 PM, Chris Zhong <zyw@rock-chips.com> wrote:
> add pmu_intmem node for suspend, add global_pwroff pinctrl.
> The pmu_intmem is used to store the resume code.
> global_pwroff is held low level at work, it would be pull to high
> when entering suspend. PMICs can get this signal, then shut down
> some power rails. So please reference the global_pwroff pinctrl
> as part of the PMIC config.
nit: I would just say to reference this in the board DTS file since
some boards need it. You could imagine this being useful to something
other than a PMIC.
> + pmu_intmem@ff720000 {
> + compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
> + reg = <0xff720000 0x4000>;
My TRM says this is 4K big. You're specifying 16K here. If it's
really 4K, it should be <0xff720000 0x1000>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v4 6/6] ARM: dts: add RK3288 suspend support
@ 2014-10-23 0:04 ` Doug Anderson
0 siblings, 0 replies; 39+ messages in thread
From: Doug Anderson @ 2014-10-23 0:04 UTC (permalink / raw
To: linux-arm-kernel
Chris,
On Tue, Oct 21, 2014 at 4:26 PM, Chris Zhong <zyw@rock-chips.com> wrote:
> add pmu_intmem node for suspend, add global_pwroff pinctrl.
> The pmu_intmem is used to store the resume code.
> global_pwroff is held low level at work, it would be pull to high
> when entering suspend. PMICs can get this signal, then shut down
> some power rails. So please reference the global_pwroff pinctrl
> as part of the PMIC config.
nit: I would just say to reference this in the board DTS file since
some boards need it. You could imagine this being useful to something
other than a PMIC.
> + pmu_intmem at ff720000 {
> + compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
> + reg = <0xff720000 0x4000>;
My TRM says this is 4K big. You're specifying 16K here. If it's
really 4K, it should be <0xff720000 0x1000>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v4 5/6] ARM: rockchip: Add pmu-sram binding
2014-10-21 23:26 ` Chris Zhong
@ 2014-10-23 0:09 ` Doug Anderson
-1 siblings, 0 replies; 39+ messages in thread
From: Doug Anderson @ 2014-10-23 0:09 UTC (permalink / raw
To: Chris Zhong
Cc: Heiko Stuebner, Mike Turquette, Ian Campbell,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Kumar Gala, Russell King, linux-rockchip, Rob Herring, Pawel Moll,
Mark Rutland, linux-arm-kernel@lists.infradead.org, Linus Walleij,
Tony Xie
Chris,
On Tue, Oct 21, 2014 at 4:26 PM, Chris Zhong <zyw@rock-chips.com> wrote:
> The pmu-sram is used to store resume code, suspend/resume need get the
> address of it. Therefore add a binding and documentation for it.
>
> Signed-off-by: Tony Xie <xxx@rock-chips.com>
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> .../devicetree/bindings/arm/rockchip/pmu-sram.txt | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt b/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
> new file mode 100644
> index 0000000..77284c0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
> @@ -0,0 +1,15 @@
> +Rockchip SRAM for pmu:
> +------------------------------
> +
> +The sram of pmu is used to store the function of resume from maskrom(the 1st
> +level loader).
It's probably best in this document to say that this is a common use
of the "pmu-sram" because it keeps power even in low power states in
the system. ...this SRAM could be used for other things as well.
> +Required node properties:
> +- compatible : should be "rockchip,rk3288-pmu-sram"
> +- reg : physical base address and the size of the registers window
> +
> +Example:
> + pmu_intmem@ff720000 {
> + compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
> + reg = <0xff720000 0x4000>;
As with the other patch, should probably change the size in the
example to 0x1000 (4K).
Otherwise this looks good to me.
-Doug
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v4 5/6] ARM: rockchip: Add pmu-sram binding
@ 2014-10-23 0:09 ` Doug Anderson
0 siblings, 0 replies; 39+ messages in thread
From: Doug Anderson @ 2014-10-23 0:09 UTC (permalink / raw
To: linux-arm-kernel
Chris,
On Tue, Oct 21, 2014 at 4:26 PM, Chris Zhong <zyw@rock-chips.com> wrote:
> The pmu-sram is used to store resume code, suspend/resume need get the
> address of it. Therefore add a binding and documentation for it.
>
> Signed-off-by: Tony Xie <xxx@rock-chips.com>
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> .../devicetree/bindings/arm/rockchip/pmu-sram.txt | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt b/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
> new file mode 100644
> index 0000000..77284c0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt
> @@ -0,0 +1,15 @@
> +Rockchip SRAM for pmu:
> +------------------------------
> +
> +The sram of pmu is used to store the function of resume from maskrom(the 1st
> +level loader).
It's probably best in this document to say that this is a common use
of the "pmu-sram" because it keeps power even in low power states in
the system. ...this SRAM could be used for other things as well.
> +Required node properties:
> +- compatible : should be "rockchip,rk3288-pmu-sram"
> +- reg : physical base address and the size of the registers window
> +
> +Example:
> + pmu_intmem at ff720000 {
> + compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
> + reg = <0xff720000 0x4000>;
As with the other patch, should probably change the size in the
example to 0x1000 (4K).
Otherwise this looks good to me.
-Doug
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v4 4/6] ARM: rockchip: add suspend and resume for RK3288
@ 2014-10-24 4:44 ` Doug Anderson
0 siblings, 0 replies; 39+ messages in thread
From: Doug Anderson @ 2014-10-24 4:44 UTC (permalink / raw
To: Chris Zhong
Cc: Heiko Stuebner, Mike Turquette, Ian Campbell,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Kumar Gala, Russell King, linux-rockchip, Rob Herring, Pawel Moll,
Mark Rutland, linux-arm-kernel@lists.infradead.org, Linus Walleij,
Tony Xie
Chris,
On Tue, Oct 21, 2014 at 4:25 PM, Chris Zhong <zyw@rock-chips.com> wrote:
> +static inline void rk3288_copy_data_to_sram(void)
> +{
> + u32 resume_code_size = (u32)&rkpm_bootdata_cpu_code -
> + (u32)rockchip_slp_cpu_resume + 4;
> +
> + /* save root sram data in ddr mem */
> + memcpy(rk3288_bootram_base, bootram_save_data, SZ_4K);
I swore we looked at this before, but the above memcpy is backwards.
> + /* move resume code and data to bootsram */
> + memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
> + resume_code_size);
> +}
> +
> +static inline void rk3288_restore_original_sram(void)
> +{
> + memcpy(bootram_save_data, rk3288_bootram_base, SZ_4K);
This one too.
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v4 4/6] ARM: rockchip: add suspend and resume for RK3288
@ 2014-10-24 4:44 ` Doug Anderson
0 siblings, 0 replies; 39+ messages in thread
From: Doug Anderson @ 2014-10-24 4:44 UTC (permalink / raw
To: Chris Zhong
Cc: Heiko Stuebner, Mike Turquette, Ian Campbell,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Kumar Gala,
Russell King, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Rob Herring, Pawel Moll, Mark Rutland,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Linus Walleij, Tony Xie
Chris,
On Tue, Oct 21, 2014 at 4:25 PM, Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
> +static inline void rk3288_copy_data_to_sram(void)
> +{
> + u32 resume_code_size = (u32)&rkpm_bootdata_cpu_code -
> + (u32)rockchip_slp_cpu_resume + 4;
> +
> + /* save root sram data in ddr mem */
> + memcpy(rk3288_bootram_base, bootram_save_data, SZ_4K);
I swore we looked at this before, but the above memcpy is backwards.
> + /* move resume code and data to bootsram */
> + memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
> + resume_code_size);
> +}
> +
> +static inline void rk3288_restore_original_sram(void)
> +{
> + memcpy(bootram_save_data, rk3288_bootram_base, SZ_4K);
This one too.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v4 4/6] ARM: rockchip: add suspend and resume for RK3288
@ 2014-10-24 4:44 ` Doug Anderson
0 siblings, 0 replies; 39+ messages in thread
From: Doug Anderson @ 2014-10-24 4:44 UTC (permalink / raw
To: linux-arm-kernel
Chris,
On Tue, Oct 21, 2014 at 4:25 PM, Chris Zhong <zyw@rock-chips.com> wrote:
> +static inline void rk3288_copy_data_to_sram(void)
> +{
> + u32 resume_code_size = (u32)&rkpm_bootdata_cpu_code -
> + (u32)rockchip_slp_cpu_resume + 4;
> +
> + /* save root sram data in ddr mem */
> + memcpy(rk3288_bootram_base, bootram_save_data, SZ_4K);
I swore we looked at this before, but the above memcpy is backwards.
> + /* move resume code and data to bootsram */
> + memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
> + resume_code_size);
> +}
> +
> +static inline void rk3288_restore_original_sram(void)
> +{
> + memcpy(bootram_save_data, rk3288_bootram_base, SZ_4K);
This one too.
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v4 5/6] ARM: rockchip: Add pmu-sram binding
2014-10-21 23:26 ` Chris Zhong
@ 2014-10-27 17:46 ` Doug Anderson
-1 siblings, 0 replies; 39+ messages in thread
From: Doug Anderson @ 2014-10-27 17:46 UTC (permalink / raw
To: Chris Zhong
Cc: Heiko Stuebner, Mike Turquette, Ian Campbell,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Kumar Gala, Russell King, linux-rockchip, Rob Herring, Pawel Moll,
Mark Rutland, linux-arm-kernel@lists.infradead.org, Linus Walleij,
Tony Xie
Chris,
On Tue, Oct 21, 2014 at 4:26 PM, Chris Zhong <zyw@rock-chips.com> wrote:
> The pmu-sram is used to store resume code, suspend/resume need get the
> address of it. Therefore add a binding and documentation for it.
>
> Signed-off-by: Tony Xie <xxx@rock-chips.com>
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> .../devicetree/bindings/arm/rockchip/pmu-sram.txt | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
Reviewed-by: Doug Anderson <dianders@chromium.org>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v4 5/6] ARM: rockchip: Add pmu-sram binding
@ 2014-10-27 17:46 ` Doug Anderson
0 siblings, 0 replies; 39+ messages in thread
From: Doug Anderson @ 2014-10-27 17:46 UTC (permalink / raw
To: linux-arm-kernel
Chris,
On Tue, Oct 21, 2014 at 4:26 PM, Chris Zhong <zyw@rock-chips.com> wrote:
> The pmu-sram is used to store resume code, suspend/resume need get the
> address of it. Therefore add a binding and documentation for it.
>
> Signed-off-by: Tony Xie <xxx@rock-chips.com>
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> .../devicetree/bindings/arm/rockchip/pmu-sram.txt | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
Reviewed-by: Doug Anderson <dianders@chromium.org>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v4 1/6] pinctrl: rockchip: add suspend/resume functions
2014-10-21 23:19 ` Chris Zhong
@ 2014-10-28 16:23 ` Linus Walleij
-1 siblings, 0 replies; 39+ messages in thread
From: Linus Walleij @ 2014-10-28 16:23 UTC (permalink / raw
To: Chris Zhong
Cc: Heiko Stuebner, Mike Turquette, Ian Campbell, Doug Anderson,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Kumar Gala, Russell King, linux-rockchip, Rob Herring, Pawel Moll,
Mark Rutland, linux-arm-kernel@lists.infradead.org
On Wed, Oct 22, 2014 at 1:19 AM, Chris Zhong <zyw@rock-chips.com> wrote:
> From: Chris <zyw@rock-chips.com>
>
> support suspend/resume of pinctrl, it allows handling sleep mode
> for hogged pins in pinctrl
>
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Looks good but I'm delegating to Heiko to collect and review patches
on the Rockchip pin control driver.
I will point out if I see something immediately disturbing.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v4 1/6] pinctrl: rockchip: add suspend/resume functions
@ 2014-10-28 16:23 ` Linus Walleij
0 siblings, 0 replies; 39+ messages in thread
From: Linus Walleij @ 2014-10-28 16:23 UTC (permalink / raw
To: linux-arm-kernel
On Wed, Oct 22, 2014 at 1:19 AM, Chris Zhong <zyw@rock-chips.com> wrote:
> From: Chris <zyw@rock-chips.com>
>
> support suspend/resume of pinctrl, it allows handling sleep mode
> for hogged pins in pinctrl
>
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Looks good but I'm delegating to Heiko to collect and review patches
on the Rockchip pin control driver.
I will point out if I see something immediately disturbing.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 39+ messages in thread
end of thread, other threads:[~2014-10-28 16:23 UTC | newest]
Thread overview: 39+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-10-21 23:17 [PATCH v4 0/6] this is the 1st version of suspend. RK3288 can shut down the cpu, gpu and Chris Zhong
2014-10-21 23:17 ` Chris Zhong
2014-10-21 23:19 ` [PATCH v4 1/6] pinctrl: rockchip: add suspend/resume functions Chris Zhong
2014-10-21 23:19 ` Chris Zhong
2014-10-22 4:19 ` Doug Anderson
2014-10-22 4:19 ` Doug Anderson
2014-10-28 16:23 ` Linus Walleij
2014-10-28 16:23 ` Linus Walleij
2014-10-21 23:19 ` [PATCH v4 2/6] pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume Chris Zhong
2014-10-21 23:19 ` Chris Zhong
2014-10-21 23:19 ` Chris Zhong
2014-10-22 4:33 ` Doug Anderson
2014-10-22 4:33 ` Doug Anderson
2014-10-22 4:33 ` Doug Anderson
2014-10-21 23:25 ` [PATCH v4 3/6] clk: rockchip: RK3288: add suspend and resume Chris Zhong
2014-10-21 23:25 ` Chris Zhong
2014-10-21 23:25 ` Chris Zhong
2014-10-22 4:58 ` Doug Anderson
2014-10-22 4:58 ` Doug Anderson
2014-10-22 4:58 ` Doug Anderson
2014-10-21 23:25 ` [PATCH v4 4/6] ARM: rockchip: add suspend and resume for RK3288 Chris Zhong
2014-10-21 23:25 ` Chris Zhong
2014-10-22 5:01 ` Doug Anderson
2014-10-22 5:01 ` Doug Anderson
2014-10-24 4:44 ` Doug Anderson
2014-10-24 4:44 ` Doug Anderson
2014-10-24 4:44 ` Doug Anderson
2014-10-21 23:26 ` [PATCH v4 5/6] ARM: rockchip: Add pmu-sram binding Chris Zhong
2014-10-21 23:26 ` Chris Zhong
2014-10-21 23:26 ` Chris Zhong
2014-10-23 0:09 ` Doug Anderson
2014-10-23 0:09 ` Doug Anderson
2014-10-27 17:46 ` Doug Anderson
2014-10-27 17:46 ` Doug Anderson
2014-10-21 23:26 ` [PATCH v4 6/6] ARM: dts: add RK3288 suspend support Chris Zhong
2014-10-21 23:26 ` Chris Zhong
2014-10-21 23:26 ` Chris Zhong
2014-10-23 0:04 ` Doug Anderson
2014-10-23 0:04 ` Doug Anderson
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