* [U-Boot] [PATCH 0/3] Makefile & x86 - Move to generic include/asm/arch/asm-offsets.h
@ 2011-08-28 13:03 Graeme Russ
2011-08-28 13:03 ` [U-Boot] [PATCH 1/3] Makefile: Add generic build rules for include/asm/arch/asm-offsets.h Graeme Russ
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Graeme Russ @ 2011-08-28 13:03 UTC (permalink / raw
To: u-boot
This series creates build rules to create (and clean)
include/asm/arch/asm-offsets.h from an asm-offsets.c file located in the
SoC directory. In particular, the new rules will skip creating the
asm-offsets.h file if the SoC does not have an asm-offsets.c file
Big Fat Note: I have not tested this on ARM which needs to be looked at
closely as the SoC files are one level deeper than where sc520 sits under
x86
Graeme Russ (3):
Makefile: Add generic build rules for include/asm/arch/asm-offsets.h
x86: Rename include/asm/ic to include/asm/arch-sc520
sc520: Create arch asm-offsets
Makefile | 22 ++-
arch/x86/cpu/Makefile | 3 +
arch/x86/cpu/sc520/Makefile | 2 +
arch/x86/cpu/sc520/asm-offsets.c | 45 ++++
arch/x86/cpu/sc520/sc520.c | 2 +-
arch/x86/cpu/sc520/sc520_car.S | 5 +-
arch/x86/cpu/sc520/sc520_pci.c | 4 +-
arch/x86/cpu/sc520/sc520_reset.c | 2 +-
arch/x86/cpu/sc520/sc520_sdram.c | 2 +-
arch/x86/cpu/sc520/sc520_ssi.c | 4 +-
arch/x86/cpu/sc520/sc520_timer.c | 2 +-
arch/x86/cpu/start.S | 3 +-
arch/x86/include/asm/arch-sc520/pci.h | 79 ++++++
arch/x86/include/asm/arch-sc520/sc520.h | 372 +++++++++++++++++++++++++++++
arch/x86/include/asm/arch-sc520/ssi.h | 34 +++
arch/x86/include/asm/global_data.h | 19 --
arch/x86/include/asm/ic/pci.h | 79 ------
arch/x86/include/asm/ic/sc520.h | 398 -------------------------------
arch/x86/include/asm/ic/ssi.h | 34 ---
arch/x86/lib/zimage.c | 1 -
board/eNET/eNET.c | 2 +-
board/eNET/eNET_pci.c | 2 +-
board/eNET/eNET_start16.S | 9 +-
23 files changed, 574 insertions(+), 551 deletions(-)
create mode 100644 arch/x86/cpu/sc520/asm-offsets.c
create mode 100644 arch/x86/include/asm/arch-sc520/pci.h
create mode 100644 arch/x86/include/asm/arch-sc520/sc520.h
create mode 100644 arch/x86/include/asm/arch-sc520/ssi.h
delete mode 100644 arch/x86/include/asm/ic/pci.h
delete mode 100644 arch/x86/include/asm/ic/sc520.h
delete mode 100644 arch/x86/include/asm/ic/ssi.h
--
1.7.5.2.317.g391b14
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH 1/3] Makefile: Add generic build rules for include/asm/arch/asm-offsets.h
2011-08-28 13:03 [U-Boot] [PATCH 0/3] Makefile & x86 - Move to generic include/asm/arch/asm-offsets.h Graeme Russ
@ 2011-08-28 13:03 ` Graeme Russ
2011-10-17 20:01 ` Wolfgang Denk
2011-10-21 21:25 ` Albert ARIBAUD
2011-08-28 13:03 ` [U-Boot] [PATCH 2/3] x86: Rename include/asm/ic to include/asm/arch-sc520 Graeme Russ
` (2 subsequent siblings)
3 siblings, 2 replies; 7+ messages in thread
From: Graeme Russ @ 2011-08-28 13:03 UTC (permalink / raw
To: u-boot
Add three features to the top-level makefile:
- Add include/asm/arch/asm-offsets.h as a dependency of the 'depend'
target to eliminate 'file does not exist' errors during dependency
building
- Skip generation of include/asm/arch/asm-offsets.h if the source file
($(CPUDIR)/$(SOC)/asm-offsets.c) does not exist
- Add removal of arch specific asm-offsets.s and asm-offsets.h files to
the 'clean' target
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
Big Fat Note: I have not tested this on ARM which needs to be looked at
closely as the SoC files are one level deeper than where sc520 sits under
x86
Makefile | 24 ++++++++++++++++++++++--
1 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/Makefile b/Makefile
index 03d80b7..049b169 100644
--- a/Makefile
+++ b/Makefile
@@ -464,7 +464,8 @@ updater:
# parallel sub-makes creating .depend files simultaneously.
depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) \
$(obj)include/autoconf.mk \
- $(obj)include/generated/generic-asm-offsets.h
+ $(obj)include/generated/generic-asm-offsets.h \
+ $(obj)include/asm/arch/asm-offsets.h
for dir in $(SUBDIRS) $(CPUDIR) $(dir $(LDSCRIPT)) ; do \
$(MAKE) -C $$dir _depend ; done
@@ -527,6 +528,23 @@ $(obj)lib/asm-offsets.s: $(obj)include/autoconf.mk.dep \
$(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
-o $@ $(src)lib/asm-offsets.c -c -S
+$(obj)include/asm/arch/asm-offsets.h: $(TOPDIR)/include/autoconf.mk.dep \
+ $(if $(wildcard $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.c), \
+ $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.s,)
+ @echo Generating $@
+ $(if $(wildcard $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.c), \
+ tools/scripts/make-asm-offsets $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.s $@ \
+ , at echo $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.c does not exist - skipping)
+
+$(TOPDIR)$(CPUDIR)/$(SOC)/asm-offsets.s: $(TOPDIR)/include/autoconf.mk.dep \
+ $(if $(wildcard $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.c), \
+ $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.c,)
+ $(if $(wildcard $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.c), \
+ $(CC) -DDO_DEPS_ONLY \
+ $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
+ -o $@ $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.c -c -S \
+ , at echo $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.c does not exist - skipping)
+
#########################################################################
else # !config.mk
all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
@@ -1019,7 +1037,9 @@ clean:
$(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds \
$(obj)u-boot.lds \
$(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] \
- $(obj)arch/blackfin/cpu/init.{lds,elf}
+ $(obj)arch/blackfin/cpu/init.{lds,elf} \
+ $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.s \
+ $(TOPDIR)/include/asm/arch/asm-offsets.h
@rm -f $(obj)include/bmp_logo.h
@rm -f $(obj)lib/asm-offsets.s
@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map}
--
1.7.5.2.317.g391b14
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH 2/3] x86: Rename include/asm/ic to include/asm/arch-sc520
2011-08-28 13:03 [U-Boot] [PATCH 0/3] Makefile & x86 - Move to generic include/asm/arch/asm-offsets.h Graeme Russ
2011-08-28 13:03 ` [U-Boot] [PATCH 1/3] Makefile: Add generic build rules for include/asm/arch/asm-offsets.h Graeme Russ
@ 2011-08-28 13:03 ` Graeme Russ
2011-08-28 13:03 ` [U-Boot] [PATCH 3/3] sc520: Create arch asm-offsets Graeme Russ
2011-08-30 17:51 ` [U-Boot] [PATCH 0/3] Makefile & x86 - Move to generic include/asm/arch/asm-offsets.h Mike Frysinger
3 siblings, 0 replies; 7+ messages in thread
From: Graeme Russ @ 2011-08-28 13:03 UTC (permalink / raw
To: u-boot
Also include some trivial related cleanups
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
arch/x86/cpu/sc520/sc520.c | 2 +-
arch/x86/cpu/sc520/sc520_car.S | 2 +-
arch/x86/cpu/sc520/sc520_pci.c | 4 +-
arch/x86/cpu/sc520/sc520_reset.c | 2 +-
arch/x86/cpu/sc520/sc520_sdram.c | 2 +-
arch/x86/cpu/sc520/sc520_ssi.c | 4 +-
arch/x86/cpu/sc520/sc520_timer.c | 2 +-
arch/x86/include/asm/arch-sc520/pci.h | 79 ++++++
arch/x86/include/asm/arch-sc520/sc520.h | 398 +++++++++++++++++++++++++++++++
arch/x86/include/asm/arch-sc520/ssi.h | 34 +++
arch/x86/include/asm/ic/pci.h | 79 ------
arch/x86/include/asm/ic/sc520.h | 398 -------------------------------
arch/x86/include/asm/ic/ssi.h | 34 ---
arch/x86/lib/zimage.c | 1 -
board/eNET/eNET.c | 2 +-
board/eNET/eNET_pci.c | 2 +-
board/eNET/eNET_start16.S | 4 +-
17 files changed, 523 insertions(+), 526 deletions(-)
create mode 100644 arch/x86/include/asm/arch-sc520/pci.h
create mode 100644 arch/x86/include/asm/arch-sc520/sc520.h
create mode 100644 arch/x86/include/asm/arch-sc520/ssi.h
delete mode 100644 arch/x86/include/asm/ic/pci.h
delete mode 100644 arch/x86/include/asm/ic/sc520.h
delete mode 100644 arch/x86/include/asm/ic/ssi.h
diff --git a/arch/x86/cpu/sc520/sc520.c b/arch/x86/cpu/sc520/sc520.c
index e37c403..4892c01 100644
--- a/arch/x86/cpu/sc520/sc520.c
+++ b/arch/x86/cpu/sc520/sc520.c
@@ -27,7 +27,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/processor-flags.h>
-#include <asm/ic/sc520.h>
+#include <asm/arch/sc520.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/x86/cpu/sc520/sc520_car.S b/arch/x86/cpu/sc520/sc520_car.S
index a33f94f..7cac4d1 100644
--- a/arch/x86/cpu/sc520/sc520_car.S
+++ b/arch/x86/cpu/sc520/sc520_car.S
@@ -23,7 +23,7 @@
#include <config.h>
#include <asm/processor-flags.h>
-#include <asm/ic/sc520.h>
+#include <asm/arch/sc520.h>
.section .text
diff --git a/arch/x86/cpu/sc520/sc520_pci.c b/arch/x86/cpu/sc520/sc520_pci.c
index 32d4802..e26793a 100644
--- a/arch/x86/cpu/sc520/sc520_pci.c
+++ b/arch/x86/cpu/sc520/sc520_pci.c
@@ -28,8 +28,8 @@
#include <pci.h>
#include <asm/io.h>
#include <asm/pci.h>
-#include <asm/ic/pci.h>
-#include <asm/ic/sc520.h>
+#include <asm/arch/pci.h>
+#include <asm/arch/sc520.h>
static struct {
u8 priority;
diff --git a/arch/x86/cpu/sc520/sc520_reset.c b/arch/x86/cpu/sc520/sc520_reset.c
index 18890c3..137af97 100644
--- a/arch/x86/cpu/sc520/sc520_reset.c
+++ b/arch/x86/cpu/sc520/sc520_reset.c
@@ -26,7 +26,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/ic/sc520.h>
+#include <asm/arch/sc520.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/x86/cpu/sc520/sc520_sdram.c b/arch/x86/cpu/sc520/sc520_sdram.c
index f3623f5..57e4e7d 100644
--- a/arch/x86/cpu/sc520/sc520_sdram.c
+++ b/arch/x86/cpu/sc520/sc520_sdram.c
@@ -24,7 +24,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/processor-flags.h>
-#include <asm/ic/sc520.h>
+#include <asm/arch/sc520.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/x86/cpu/sc520/sc520_ssi.c b/arch/x86/cpu/sc520/sc520_ssi.c
index 47aa80b..3a6a858 100644
--- a/arch/x86/cpu/sc520/sc520_ssi.c
+++ b/arch/x86/cpu/sc520/sc520_ssi.c
@@ -23,8 +23,8 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/ic/ssi.h>
-#include <asm/ic/sc520.h>
+#include <asm/arch/ssi.h>
+#include <asm/arch/sc520.h>
int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
{
diff --git a/arch/x86/cpu/sc520/sc520_timer.c b/arch/x86/cpu/sc520/sc520_timer.c
index 5cccda1..05bc9c1 100644
--- a/arch/x86/cpu/sc520/sc520_timer.c
+++ b/arch/x86/cpu/sc520/sc520_timer.c
@@ -27,7 +27,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/interrupt.h>
-#include <asm/ic/sc520.h>
+#include <asm/arch/sc520.h>
void sc520_timer_isr(void)
{
diff --git a/arch/x86/include/asm/arch-sc520/pci.h b/arch/x86/include/asm/arch-sc520/pci.h
new file mode 100644
index 0000000..12ba656
--- /dev/null
+++ b/arch/x86/include/asm/arch-sc520/pci.h
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engstr?m, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_IC_SC520_PCI_H_
+#define _ASM_IC_SC520_PCI_H_ 1
+
+/* bus mapping constants (used for PCI core initialization) */ /* bus mapping constants */
+#define SC520_REG_ADDR 0x00000cf8
+#define SC520_REG_DATA 0x00000cfc
+
+#define SC520_ISA_MEM_PHYS 0x00000000
+#define SC520_ISA_MEM_BUS 0x00000000
+#define SC520_ISA_MEM_SIZE 0x01000000
+
+#define SC520_ISA_IO_PHYS 0x00000000
+#define SC520_ISA_IO_BUS 0x00000000
+#define SC520_ISA_IO_SIZE 0x00001000
+
+/* PCI I/O space from 0x1000 to 0xdfff
+ * (make 0xe000-0xfdff available for stuff like PCCard boot) */
+#define SC520_PCI_IO_PHYS 0x00001000
+#define SC520_PCI_IO_BUS 0x00001000
+#define SC520_PCI_IO_SIZE 0x0000d000
+
+/* system memory from 0x00000000 to 0x0fffffff */
+#define SC520_PCI_MEMORY_PHYS 0x00000000
+#define SC520_PCI_MEMORY_BUS 0x00000000
+#define SC520_PCI_MEMORY_SIZE 0x10000000
+
+/* PCI bus memory from 0x10000000 to 0x26ffffff
+ * (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */
+#define SC520_PCI_MEM_PHYS 0x10000000
+#define SC520_PCI_MEM_BUS 0x10000000
+#define SC520_PCI_MEM_SIZE 0x17000000
+
+/* pin number used for PCI interrupt mappings */
+#define SC520_PCI_INTA 0
+#define SC520_PCI_INTB 1
+#define SC520_PCI_INTC 2
+#define SC520_PCI_INTD 3
+#define SC520_PCI_GPIRQ0 4
+#define SC520_PCI_GPIRQ1 5
+#define SC520_PCI_GPIRQ2 6
+#define SC520_PCI_GPIRQ3 7
+#define SC520_PCI_GPIRQ4 8
+#define SC520_PCI_GPIRQ5 9
+#define SC520_PCI_GPIRQ6 10
+#define SC520_PCI_GPIRQ7 11
+#define SC520_PCI_GPIRQ8 12
+#define SC520_PCI_GPIRQ9 13
+#define SC520_PCI_GPIRQ10 14
+
+extern int sc520_pci_ints[];
+
+void pci_sc520_init(struct pci_controller *hose);
+int pci_set_regions(struct pci_controller *hose);
+int pci_sc520_set_irq(int pci_pin, int irq);
+
+#endif
diff --git a/arch/x86/include/asm/arch-sc520/sc520.h b/arch/x86/include/asm/arch-sc520/sc520.h
new file mode 100644
index 0000000..5ac9bb8
--- /dev/null
+++ b/arch/x86/include/asm/arch-sc520/sc520.h
@@ -0,0 +1,398 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engstr?m, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_IC_SC520_H_
+#define _ASM_IC_SC520_H_ 1
+
+#ifndef __ASSEMBLY__
+
+void init_sc520(void);
+unsigned long init_sc520_dram(void);
+void sc520_udelay(unsigned long usec);
+
+/* Memory mapped configuration registers */
+typedef struct sc520_mmcr {
+ u16 revid; /* ElanSC520 microcontroller revision id */
+ u8 cpuctl; /* am5x86 CPU control */
+
+ u8 pad_0x003[0x0d];
+
+ u8 drcctl; /* SDRAM control */
+ u8 pad_0x011[0x01];
+ u8 drctmctl; /* SDRAM timing control */
+ u8 pad_0x013[0x01];
+ u16 drccfg; /* SDRAM bank configuration*/
+ u8 pad_0x016[0x02];
+ u32 drcbendadr; /* SDRAM bank 0-3 ending address*/
+ u8 pad_0x01c[0x04];
+ u8 eccctl; /* ECC control */
+ u8 eccsta; /* ECC status */
+ u8 eccckbpos; /* ECC check bit position */
+ u8 ecccktest; /* ECC Check Code Test */
+ u32 eccsbadd; /* ECC single-bit error address */
+ u32 eccmbadd; /* ECC multi-bit error address */
+
+ u8 pad_0x02c[0x14];
+
+ u8 dbctl; /* SDRAM buffer control */
+
+ u8 pad_0x041[0x0f];
+
+ u16 bootcsctl; /* /BOOTCS control */
+ u8 pad_0x052[0x02];
+ u16 romcs1ctl; /* /ROMCS1 control */
+ u16 romcs2ctl; /* /ROMCS2 control */
+
+ u8 pad_0x058[0x08];
+
+ u16 hbctl; /* host bridge control */
+ u16 hbtgtirqctl; /* host bridge target interrupt control */
+ u16 hbtgtirqsta; /* host bridge target interrupt status */
+ u16 hbmstirqctl; /* host bridge target interrupt control */
+ u16 hbmstirqsta; /* host bridge master interrupt status */
+ u8 pad_0x06a[0x02];
+ u32 mstintadd; /* host bridge master interrupt address */
+
+ u8 sysarbctl; /* system arbiter control */
+ u8 pciarbsta; /* PCI bus arbiter status */
+ u16 sysarbmenb; /* system arbiter master enable */
+ u32 arbprictl; /* arbiter priority control */
+
+ u8 pad_0x078[0x08];
+
+ u8 adddecctl; /* address decode control */
+ u8 pad_0x081[0x01];
+ u16 wpvsta; /* write-protect violation status */
+ u8 pad_0x084[0x04];
+ u32 par[16]; /* programmable address regions */
+
+ u8 pad_0x0c8[0x0b38];
+
+ u8 gpecho; /* GP echo mode */
+ u8 gpcsdw; /* GP chip select data width */
+ u16 gpcsqual; /* GP chip select qualification */
+ u8 pad_0xc04[0x4];
+ u8 gpcsrt; /* GP chip select recovery time */
+ u8 gpcspw; /* GP chip select pulse width */
+ u8 gpcsoff; /* GP chip select offset */
+ u8 gprdw; /* GP read pulse width */
+ u8 gprdoff; /* GP read offset */
+ u8 gpwrw; /* GP write pulse width */
+ u8 gpwroff; /* GP write offset */
+ u8 gpalew; /* GP ale pulse width */
+ u8 gpaleoff; /* GP ale offset */
+
+ u8 pad_0xc11[0x0f];
+
+ u16 piopfs15_0; /* PIO15-PIO0 pin function select */
+ u16 piopfs31_16; /* PIO31-PIO16 pin function select */
+ u8 cspfs; /* chip select pin function select */
+ u8 pad_0xc25[0x01];
+ u8 clksel; /* clock select */
+ u8 pad_0xc27[0x01];
+ u16 dsctl; /* drive strength control */
+ u16 piodir15_0; /* PIO15-PIO0 direction */
+ u16 piodir31_16; /* PIO31-PIO16 direction */
+ u8 pad_0xc2e[0x02];
+ u16 piodata15_0 ; /* PIO15-PIO0 data */
+ u16 piodata31_16; /* PIO31-PIO16 data */
+ u16 pioset15_0; /* PIO15-PIO0 set */
+ u16 pioset31_16; /* PIO31-PIO16 set */
+ u16 pioclr15_0; /* PIO15-PIO0 clear */
+ u16 pioclr31_16; /* PIO31-PIO16 clear */
+
+ u8 pad_0xc3c[0x24];
+
+ u16 swtmrmilli; /* software timer millisecond count */
+ u16 swtmrmicro; /* software timer microsecond count */
+ u8 swtmrcfg; /* software timer configuration */
+
+ u8 pad_0xc65[0x0b];
+
+ u8 gptmrsta; /* GP timers status register */
+ u8 pad_0xc71;
+ u16 gptmr0ctl; /* GP timer 0 mode/control */
+ u16 gptmr0cnt; /* GP timer 0 count */
+ u16 gptmr0maxcmpa; /* GP timer 0 maxcount compare A */
+ u16 gptmr0maxcmpb; /* GP timer 0 maxcount compare B */
+ u16 gptmr1ctl; /* GP timer 1 mode/control */
+ u16 gptmr1cnt; /* GP timer 1 count */
+ u16 gptmr1maxcmpa; /* GP timer 1 maxcount compare A */
+ u16 gptmr1maxcmpb; /* GP timer 1 maxcount compare B*/
+ u16 gptmr2ctl; /* GP timer 2 mode/control */
+ u16 gptmr2cnt; /* GP timer 2 count */
+ u8 pad_0xc86[0x08];
+ u16 gptmr2maxcmpa; /* GP timer 2 maxcount compare A */
+
+ u8 pad_0xc90[0x20];
+
+ u16 wdtmrctl; /* watchdog timer control */
+ u16 wdtmrcntl; /* watchdog timer count low */
+ u16 wdtmrcnth; /* watchdog timer count high */
+
+ u8 pad_0xcb6[0x0a];
+
+ u8 uart1ctl; /* UART 1 general control */
+ u8 uart1sta; /* UART 1 general status */
+ u8 uart1fcrshad; /* UART 1 FIFO control shadow */
+ u8 pad_0xcc3[0x01];
+ u8 uart2ctl; /* UART 2 general control */
+ u8 uart2sta; /* UART 2 general status */
+ u8 uart2fcrshad; /* UART 2 FIFO control shadow */
+
+ u8 pad_0xcc7[0x09];
+
+ u8 ssictl; /* SSI control */
+ u8 ssixmit; /* SSI transmit */
+ u8 ssicmd; /* SSI command */
+ u8 ssista; /* SSI status */
+ u8 ssircv; /* SSI receive */
+
+ u8 pad_0xcd5[0x2b];
+
+ u8 picicr; /* interrupt control */
+ u8 pad_0xd01[0x01];
+ u8 pic_mode[3]; /* PIC interrupt mode */
+ u8 pad_0xd05[0x03];
+ u16 swint16_1; /* software interrupt 16-1 control */
+ u8 swint22_17; /* software interrupt 22-17/NMI control */
+ u8 pad_0xd0b[0x05];
+ u16 intpinpol; /* interrupt pin polarity */
+ u8 pad_0xd12[0x02];
+ u16 pcihostmap; /* PCI host bridge interrupt mapping */
+ u8 pad_0xd16[0x02];
+ u16 eccmap; /* ECC interrupt mapping */
+ u8 gp_tmr_int_map[3]; /* GP timer interrupt mapping */
+ u8 pad_0xd1d[0x03];
+ u8 pit_int_map[3]; /* PIT interrupt mapping */
+ u8 pad_0xd23[0x05];
+ u8 uart_int_map[2]; /* UART interrupt mapping */
+ u8 pad_0xd2a[0x06];
+ u8 pci_int_map[4]; /* PCI interrupt mapping (A through D)*/
+ u8 pad_0xd34[0x0c];
+ u8 dmabcintmap; /* DMA buffer chaining interrupt mapping */
+ u8 ssimap; /* SSI interrupt mapping register */
+ u8 wdtmap; /* watchdog timer interrupt mapping */
+ u8 rtcmap; /* RTC interrupt mapping register */
+ u8 wpvmap; /* write-protect interrupt mapping */
+ u8 icemap; /* AMDebug JTAG Rx/Tx interrupt mapping */
+ u8 ferrmap; /* floating point error interrupt mapping */
+ u8 pad_0xd47[0x09];
+ u8 gp_int_map[11]; /* GP IRQ interrupt mapping */
+
+ u8 pad_0xd5b[0x15];
+
+ u8 sysinfo; /* system board information */
+ u8 pad_0xd71[0x01];
+ u8 rescfg; /* reset configuration */
+ u8 pad_0xd73[0x01];
+ u8 ressta; /* reset status */
+
+ u8 pad_0xd75[0x0b];
+
+ u8 gpdmactl; /* GP-DMA Control */
+ u8 gpdmammio; /* GP-DMA memory-mapped I/O */
+ u16 gpdmaextchmapa; /* GP-DMA resource channel map a */
+ u16 gpdmaextchmapb; /* GP-DMA resource channel map b */
+ u8 gp_dma_ext_pg_0; /* GP-DMA channel extended page 0 */
+ u8 gp_dma_ext_pg_1; /* GP-DMA channel extended page 0 */
+ u8 gp_dma_ext_pg_2; /* GP-DMA channel extended page 0 */
+ u8 gp_dma_ext_pg_3; /* GP-DMA channel extended page 0 */
+ u8 gp_dma_ext_pg_5; /* GP-DMA channel extended page 0 */
+ u8 gp_dma_ext_pg_6; /* GP-DMA channel extended page 0 */
+ u8 gp_dma_ext_pg_7; /* GP-DMA channel extended page 0 */
+ u8 pad_0xd8d[0x03];
+ u8 gpdmaexttc3; /* GP-DMA channel 3 extender transfer count */
+ u8 gpdmaexttc5; /* GP-DMA channel 5 extender transfer count */
+ u8 gpdmaexttc6; /* GP-DMA channel 6 extender transfer count */
+ u8 gpdmaexttc7; /* GP-DMA channel 7 extender transfer count */
+ u8 pad_0xd94[0x4];
+ u8 gpdmabcctl; /* buffer chaining control */
+ u8 gpdmabcsta; /* buffer chaining status */
+ u8 gpdmabsintenb; /* buffer chaining interrupt enable */
+ u8 gpdmabcval; /* buffer chaining valid */
+ u8 pad_0xd9c[0x04];
+ u16 gpdmanxtaddl3; /* GP-DMA channel 3 next address low */
+ u16 gpdmanxtaddh3; /* GP-DMA channel 3 next address high */
+ u16 gpdmanxtaddl5; /* GP-DMA channel 5 next address low */
+ u16 gpdmanxtaddh5; /* GP-DMA channel 5 next address high */
+ u16 gpdmanxtaddl6; /* GP-DMA channel 6 next address low */
+ u16 gpdmanxtaddh6; /* GP-DMA channel 6 next address high */
+ u16 gpdmanxtaddl7; /* GP-DMA channel 7 next address low */
+ u16 gpdmanxtaddh7; /* GP-DMA channel 7 next address high */
+ u16 gpdmanxttcl3; /* GP-DMA channel 3 next transfer count low */
+ u16 gpdmanxttch3; /* GP-DMA channel 3 next transfer count high */
+ u16 gpdmanxttcl5; /* GP-DMA channel 5 next transfer count low */
+ u16 gpdmanxttch5; /* GP-DMA channel 5 next transfer count high */
+ u16 gpdmanxttcl6; /* GP-DMA channel 6 next transfer count low */
+ u16 gpdmanxttch6; /* GP-DMA channel 6 next transfer count high */
+ u16 gpdmanxttcl7; /* GP-DMA channel 7 next transfer count low */
+ u16 gpdmanxttch7; /* GP-DMA channel 7 next transfer count high */
+
+ u8 pad_0xdc0[0x0240];
+} sc520_mmcr_t;
+
+extern sc520_mmcr_t *sc520_mmcr;
+
+#endif
+
+/* Memory Mapped Control Registers (MMCR) Base Address */
+#define SC520_MMCR_BASE 0xfffef000
+
+/* MMCR Addresses (required for assembler code) */
+#define SC520_DRCCTL (SC520_MMCR_BASE + 0x010)
+#define SC520_DRCTMCTL (SC520_MMCR_BASE + 0x012)
+#define SC520_DRCCFG (SC520_MMCR_BASE + 0x014)
+#define SC520_DRCBENDADR (SC520_MMCR_BASE + 0x018)
+#define SC520_ECCCTL (SC520_MMCR_BASE + 0x020)
+#define SC520_DBCTL (SC520_MMCR_BASE + 0x040)
+#define SC520_ECCINT (SC520_MMCR_BASE + 0xd18)
+
+#define SC520_PAR0 (SC520_MMCR_BASE + 0x088)
+#define SC520_PAR1 (SC520_PAR0 + (0x04 * 1))
+#define SC520_PAR2 (SC520_PAR0 + (0x04 * 2))
+#define SC520_PAR3 (SC520_PAR0 + (0x04 * 3))
+#define SC520_PAR4 (SC520_PAR0 + (0x04 * 4))
+#define SC520_PAR5 (SC520_PAR0 + (0x04 * 5))
+#define SC520_PAR6 (SC520_PAR0 + (0x04 * 6))
+#define SC520_PAR7 (SC520_PAR0 + (0x04 * 7))
+#define SC520_PAR8 (SC520_PAR0 + (0x04 * 8))
+#define SC520_PAR9 (SC520_PAR0 + (0x04 * 9))
+#define SC520_PAR10 (SC520_PAR0 + (0x04 * 10))
+#define SC520_PAR11 (SC520_PAR0 + (0x04 * 11))
+#define SC520_PAR12 (SC520_PAR0 + (0x04 * 12))
+#define SC520_PAR13 (SC520_PAR0 + (0x04 * 13))
+#define SC520_PAR14 (SC520_PAR0 + (0x04 * 14))
+#define SC520_PAR15 (SC520_PAR0 + (0x04 * 15))
+
+/*
+ * PARs for maximum allowable 256MB of SDRAM @ 0x00000000
+ * Two PARs are required due to maximum PAR size of 128MB
+ * These are used in the SDRAM sizing code to disable caching
+ *
+ * 111 0 0 0 1 11111111111 00000000000000 }- 0xe3ffc000
+ * 111 0 0 0 1 11111111111 00100000000000 }- 0xe3ffc800
+ * \ / | | | | \----+----/ \-----+------/
+ * | | | | | | +---------- Start at 0x00000000
+ * | | | | | | 0x08000000
+ * | | | | | +----------------------- 128MB Region Size
+ * | | | | | ((2047 + 1) * 64kB)
+ * | | | | +------------------------------ 64kB Page Size
+ * | | | +-------------------------------- Writes Enabled
+ * | | +---------------------------------- Caching Enabled
+ * | +------------------------------------ Execution Enabled
+ * +--------------------------------------- SDRAM
+ */
+#define SC520_SDRAM1_PAR 0xe3ffc000
+#define SC520_SDRAM2_PAR 0xe3ffc800
+
+#define SC520_PAR_WRITE_DIS 0x04000000
+#define SC520_PAR_CACHE_DIS 0x08000000
+#define SC520_PAR_EXEC_DIS 0x10000000
+
+/*
+ * Programmable Address Regions to cover 256MB SDRAM (Maximum supported)
+ * required for DRAM sizing code
+ */
+
+/* MMCR Register bits (not all of them :) ) */
+
+/* SSI Stuff */
+#define CTL_CLK_SEL_4 0x00 /* Nominal Bit Rate = 8 MHz */
+#define CTL_CLK_SEL_8 0x10 /* Nominal Bit Rate = 4 MHz */
+#define CTL_CLK_SEL_16 0x20 /* Nominal Bit Rate = 2 MHz */
+#define CTL_CLK_SEL_32 0x30 /* Nominal Bit Rate = 1 MHz */
+#define CTL_CLK_SEL_64 0x40 /* Nominal Bit Rate = 512 KHz */
+#define CTL_CLK_SEL_128 0x50 /* Nominal Bit Rate = 256 KHz */
+#define CTL_CLK_SEL_256 0x60 /* Nominal Bit Rate = 128 KHz */
+#define CTL_CLK_SEL_512 0x70 /* Nominal Bit Rate = 64 KHz */
+
+#define TC_INT_ENB 0x08 /* Transaction Complete Interrupt Enable */
+#define PHS_INV_ENB 0x04 /* SSI Inverted Phase Mode Enable */
+#define CLK_INV_ENB 0x02 /* SSI Inverted Clock Mode Enable */
+#define MSBF_ENB 0x01 /* SSI Most Significant Bit First Mode Enable */
+
+#define SSICMD_CMD_SEL_XMITRCV 0x03 /* Simultaneous Transmit / Receive Transaction */
+#define SSICMD_CMD_SEL_RCV 0x02 /* Receive Transaction */
+#define SSICMD_CMD_SEL_XMIT 0x01 /* Transmit Transaction */
+#define SSISTA_BSY 0x02 /* SSI Busy */
+#define SSISTA_TC_INT 0x01 /* SSI Transaction Complete Interrupt */
+
+/* BITS for SC520_ADDDECCTL: */
+#define WPV_INT_ENB 0x80 /* Write-Protect Violation Interrupt Enable */
+#define IO_HOLE_DEST_PCI 0x10 /* I/O Hole Access Destination */
+#define RTC_DIS 0x04 /* RTC Disable */
+#define UART2_DIS 0x02 /* UART2 Disable */
+#define UART1_DIS 0x01 /* UART1 Disable */
+
+/*
+ * Defines used for SDRAM Sizing (number of columns and rows)
+ * Refer to section 10.6.4 - SDRAM Sizing Algorithm in the
+ * Elan SC520 Microcontroller User's Manual (Order #22004B)
+ */
+#define CACHELINESZ 0x00000010
+
+#define COL11_ADR 0x0e001e00
+#define COL10_ADR 0x0e000e00
+#define COL09_ADR 0x0e000600
+#define COL08_ADR 0x0e000200
+#define COL11_DATA 0x0b0b0b0b
+#define COL10_DATA 0x0a0a0a0a
+#define COL09_DATA 0x09090909
+#define COL08_DATA 0x08080808
+
+#define ROW14_ADR 0x0f000000
+#define ROW13_ADR 0x07000000
+#define ROW12_ADR 0x03000000
+#define ROW11_ADR 0x01000000
+#define ROW10_ADR 0x00000000
+#define ROW14_DATA 0x3f3f3f3f
+#define ROW13_DATA 0x1f1f1f1f
+#define ROW12_DATA 0x0f0f0f0f
+#define ROW11_DATA 0x07070707
+#define ROW10_DATA 0xaaaaaaaa
+
+/* 0x28000000 - 0x3fffffff is used by the flash banks */
+
+/* 0x40000000 - 0xffffffff is not adressable by the SC520 */
+
+/* priority numbers used for interrupt channel mappings */
+#define SC520_IRQ_DISABLED 0
+#define SC520_IRQ0 1
+#define SC520_IRQ1 2
+#define SC520_IRQ2 4 /* same as IRQ9 */
+#define SC520_IRQ3 11
+#define SC520_IRQ4 12
+#define SC520_IRQ5 13
+#define SC520_IRQ6 21
+#define SC520_IRQ7 22
+#define SC520_IRQ8 3
+#define SC520_IRQ9 4
+#define SC520_IRQ10 5
+#define SC520_IRQ11 6
+#define SC520_IRQ12 7
+#define SC520_IRQ13 8
+#define SC520_IRQ14 9
+#define SC520_IRQ15 10
+
+#endif
diff --git a/arch/x86/include/asm/arch-sc520/ssi.h b/arch/x86/include/asm/arch-sc520/ssi.h
new file mode 100644
index 0000000..bd48eab
--- /dev/null
+++ b/arch/x86/include/asm/arch-sc520/ssi.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ <graeme.russ@gmail.com>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_IC_SSI_H_
+#define _ASM_IC_SSI_H_ 1
+
+int ssi_set_interface(int, int, int, int);
+void ssi_chip_select(int);
+u8 ssi_txrx_byte(u8);
+void ssi_tx_byte(u8);
+u8 ssi_rx_byte(void);
+
+
+#endif
diff --git a/arch/x86/include/asm/ic/pci.h b/arch/x86/include/asm/ic/pci.h
deleted file mode 100644
index 12ba656..0000000
--- a/arch/x86/include/asm/ic/pci.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engstr?m, Omicron Ceti AB <daniel@omicron.se>.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _ASM_IC_SC520_PCI_H_
-#define _ASM_IC_SC520_PCI_H_ 1
-
-/* bus mapping constants (used for PCI core initialization) */ /* bus mapping constants */
-#define SC520_REG_ADDR 0x00000cf8
-#define SC520_REG_DATA 0x00000cfc
-
-#define SC520_ISA_MEM_PHYS 0x00000000
-#define SC520_ISA_MEM_BUS 0x00000000
-#define SC520_ISA_MEM_SIZE 0x01000000
-
-#define SC520_ISA_IO_PHYS 0x00000000
-#define SC520_ISA_IO_BUS 0x00000000
-#define SC520_ISA_IO_SIZE 0x00001000
-
-/* PCI I/O space from 0x1000 to 0xdfff
- * (make 0xe000-0xfdff available for stuff like PCCard boot) */
-#define SC520_PCI_IO_PHYS 0x00001000
-#define SC520_PCI_IO_BUS 0x00001000
-#define SC520_PCI_IO_SIZE 0x0000d000
-
-/* system memory from 0x00000000 to 0x0fffffff */
-#define SC520_PCI_MEMORY_PHYS 0x00000000
-#define SC520_PCI_MEMORY_BUS 0x00000000
-#define SC520_PCI_MEMORY_SIZE 0x10000000
-
-/* PCI bus memory from 0x10000000 to 0x26ffffff
- * (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */
-#define SC520_PCI_MEM_PHYS 0x10000000
-#define SC520_PCI_MEM_BUS 0x10000000
-#define SC520_PCI_MEM_SIZE 0x17000000
-
-/* pin number used for PCI interrupt mappings */
-#define SC520_PCI_INTA 0
-#define SC520_PCI_INTB 1
-#define SC520_PCI_INTC 2
-#define SC520_PCI_INTD 3
-#define SC520_PCI_GPIRQ0 4
-#define SC520_PCI_GPIRQ1 5
-#define SC520_PCI_GPIRQ2 6
-#define SC520_PCI_GPIRQ3 7
-#define SC520_PCI_GPIRQ4 8
-#define SC520_PCI_GPIRQ5 9
-#define SC520_PCI_GPIRQ6 10
-#define SC520_PCI_GPIRQ7 11
-#define SC520_PCI_GPIRQ8 12
-#define SC520_PCI_GPIRQ9 13
-#define SC520_PCI_GPIRQ10 14
-
-extern int sc520_pci_ints[];
-
-void pci_sc520_init(struct pci_controller *hose);
-int pci_set_regions(struct pci_controller *hose);
-int pci_sc520_set_irq(int pci_pin, int irq);
-
-#endif
diff --git a/arch/x86/include/asm/ic/sc520.h b/arch/x86/include/asm/ic/sc520.h
deleted file mode 100644
index 5ac9bb8..0000000
--- a/arch/x86/include/asm/ic/sc520.h
+++ /dev/null
@@ -1,398 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engstr?m, Omicron Ceti AB <daniel@omicron.se>.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _ASM_IC_SC520_H_
-#define _ASM_IC_SC520_H_ 1
-
-#ifndef __ASSEMBLY__
-
-void init_sc520(void);
-unsigned long init_sc520_dram(void);
-void sc520_udelay(unsigned long usec);
-
-/* Memory mapped configuration registers */
-typedef struct sc520_mmcr {
- u16 revid; /* ElanSC520 microcontroller revision id */
- u8 cpuctl; /* am5x86 CPU control */
-
- u8 pad_0x003[0x0d];
-
- u8 drcctl; /* SDRAM control */
- u8 pad_0x011[0x01];
- u8 drctmctl; /* SDRAM timing control */
- u8 pad_0x013[0x01];
- u16 drccfg; /* SDRAM bank configuration*/
- u8 pad_0x016[0x02];
- u32 drcbendadr; /* SDRAM bank 0-3 ending address*/
- u8 pad_0x01c[0x04];
- u8 eccctl; /* ECC control */
- u8 eccsta; /* ECC status */
- u8 eccckbpos; /* ECC check bit position */
- u8 ecccktest; /* ECC Check Code Test */
- u32 eccsbadd; /* ECC single-bit error address */
- u32 eccmbadd; /* ECC multi-bit error address */
-
- u8 pad_0x02c[0x14];
-
- u8 dbctl; /* SDRAM buffer control */
-
- u8 pad_0x041[0x0f];
-
- u16 bootcsctl; /* /BOOTCS control */
- u8 pad_0x052[0x02];
- u16 romcs1ctl; /* /ROMCS1 control */
- u16 romcs2ctl; /* /ROMCS2 control */
-
- u8 pad_0x058[0x08];
-
- u16 hbctl; /* host bridge control */
- u16 hbtgtirqctl; /* host bridge target interrupt control */
- u16 hbtgtirqsta; /* host bridge target interrupt status */
- u16 hbmstirqctl; /* host bridge target interrupt control */
- u16 hbmstirqsta; /* host bridge master interrupt status */
- u8 pad_0x06a[0x02];
- u32 mstintadd; /* host bridge master interrupt address */
-
- u8 sysarbctl; /* system arbiter control */
- u8 pciarbsta; /* PCI bus arbiter status */
- u16 sysarbmenb; /* system arbiter master enable */
- u32 arbprictl; /* arbiter priority control */
-
- u8 pad_0x078[0x08];
-
- u8 adddecctl; /* address decode control */
- u8 pad_0x081[0x01];
- u16 wpvsta; /* write-protect violation status */
- u8 pad_0x084[0x04];
- u32 par[16]; /* programmable address regions */
-
- u8 pad_0x0c8[0x0b38];
-
- u8 gpecho; /* GP echo mode */
- u8 gpcsdw; /* GP chip select data width */
- u16 gpcsqual; /* GP chip select qualification */
- u8 pad_0xc04[0x4];
- u8 gpcsrt; /* GP chip select recovery time */
- u8 gpcspw; /* GP chip select pulse width */
- u8 gpcsoff; /* GP chip select offset */
- u8 gprdw; /* GP read pulse width */
- u8 gprdoff; /* GP read offset */
- u8 gpwrw; /* GP write pulse width */
- u8 gpwroff; /* GP write offset */
- u8 gpalew; /* GP ale pulse width */
- u8 gpaleoff; /* GP ale offset */
-
- u8 pad_0xc11[0x0f];
-
- u16 piopfs15_0; /* PIO15-PIO0 pin function select */
- u16 piopfs31_16; /* PIO31-PIO16 pin function select */
- u8 cspfs; /* chip select pin function select */
- u8 pad_0xc25[0x01];
- u8 clksel; /* clock select */
- u8 pad_0xc27[0x01];
- u16 dsctl; /* drive strength control */
- u16 piodir15_0; /* PIO15-PIO0 direction */
- u16 piodir31_16; /* PIO31-PIO16 direction */
- u8 pad_0xc2e[0x02];
- u16 piodata15_0 ; /* PIO15-PIO0 data */
- u16 piodata31_16; /* PIO31-PIO16 data */
- u16 pioset15_0; /* PIO15-PIO0 set */
- u16 pioset31_16; /* PIO31-PIO16 set */
- u16 pioclr15_0; /* PIO15-PIO0 clear */
- u16 pioclr31_16; /* PIO31-PIO16 clear */
-
- u8 pad_0xc3c[0x24];
-
- u16 swtmrmilli; /* software timer millisecond count */
- u16 swtmrmicro; /* software timer microsecond count */
- u8 swtmrcfg; /* software timer configuration */
-
- u8 pad_0xc65[0x0b];
-
- u8 gptmrsta; /* GP timers status register */
- u8 pad_0xc71;
- u16 gptmr0ctl; /* GP timer 0 mode/control */
- u16 gptmr0cnt; /* GP timer 0 count */
- u16 gptmr0maxcmpa; /* GP timer 0 maxcount compare A */
- u16 gptmr0maxcmpb; /* GP timer 0 maxcount compare B */
- u16 gptmr1ctl; /* GP timer 1 mode/control */
- u16 gptmr1cnt; /* GP timer 1 count */
- u16 gptmr1maxcmpa; /* GP timer 1 maxcount compare A */
- u16 gptmr1maxcmpb; /* GP timer 1 maxcount compare B*/
- u16 gptmr2ctl; /* GP timer 2 mode/control */
- u16 gptmr2cnt; /* GP timer 2 count */
- u8 pad_0xc86[0x08];
- u16 gptmr2maxcmpa; /* GP timer 2 maxcount compare A */
-
- u8 pad_0xc90[0x20];
-
- u16 wdtmrctl; /* watchdog timer control */
- u16 wdtmrcntl; /* watchdog timer count low */
- u16 wdtmrcnth; /* watchdog timer count high */
-
- u8 pad_0xcb6[0x0a];
-
- u8 uart1ctl; /* UART 1 general control */
- u8 uart1sta; /* UART 1 general status */
- u8 uart1fcrshad; /* UART 1 FIFO control shadow */
- u8 pad_0xcc3[0x01];
- u8 uart2ctl; /* UART 2 general control */
- u8 uart2sta; /* UART 2 general status */
- u8 uart2fcrshad; /* UART 2 FIFO control shadow */
-
- u8 pad_0xcc7[0x09];
-
- u8 ssictl; /* SSI control */
- u8 ssixmit; /* SSI transmit */
- u8 ssicmd; /* SSI command */
- u8 ssista; /* SSI status */
- u8 ssircv; /* SSI receive */
-
- u8 pad_0xcd5[0x2b];
-
- u8 picicr; /* interrupt control */
- u8 pad_0xd01[0x01];
- u8 pic_mode[3]; /* PIC interrupt mode */
- u8 pad_0xd05[0x03];
- u16 swint16_1; /* software interrupt 16-1 control */
- u8 swint22_17; /* software interrupt 22-17/NMI control */
- u8 pad_0xd0b[0x05];
- u16 intpinpol; /* interrupt pin polarity */
- u8 pad_0xd12[0x02];
- u16 pcihostmap; /* PCI host bridge interrupt mapping */
- u8 pad_0xd16[0x02];
- u16 eccmap; /* ECC interrupt mapping */
- u8 gp_tmr_int_map[3]; /* GP timer interrupt mapping */
- u8 pad_0xd1d[0x03];
- u8 pit_int_map[3]; /* PIT interrupt mapping */
- u8 pad_0xd23[0x05];
- u8 uart_int_map[2]; /* UART interrupt mapping */
- u8 pad_0xd2a[0x06];
- u8 pci_int_map[4]; /* PCI interrupt mapping (A through D)*/
- u8 pad_0xd34[0x0c];
- u8 dmabcintmap; /* DMA buffer chaining interrupt mapping */
- u8 ssimap; /* SSI interrupt mapping register */
- u8 wdtmap; /* watchdog timer interrupt mapping */
- u8 rtcmap; /* RTC interrupt mapping register */
- u8 wpvmap; /* write-protect interrupt mapping */
- u8 icemap; /* AMDebug JTAG Rx/Tx interrupt mapping */
- u8 ferrmap; /* floating point error interrupt mapping */
- u8 pad_0xd47[0x09];
- u8 gp_int_map[11]; /* GP IRQ interrupt mapping */
-
- u8 pad_0xd5b[0x15];
-
- u8 sysinfo; /* system board information */
- u8 pad_0xd71[0x01];
- u8 rescfg; /* reset configuration */
- u8 pad_0xd73[0x01];
- u8 ressta; /* reset status */
-
- u8 pad_0xd75[0x0b];
-
- u8 gpdmactl; /* GP-DMA Control */
- u8 gpdmammio; /* GP-DMA memory-mapped I/O */
- u16 gpdmaextchmapa; /* GP-DMA resource channel map a */
- u16 gpdmaextchmapb; /* GP-DMA resource channel map b */
- u8 gp_dma_ext_pg_0; /* GP-DMA channel extended page 0 */
- u8 gp_dma_ext_pg_1; /* GP-DMA channel extended page 0 */
- u8 gp_dma_ext_pg_2; /* GP-DMA channel extended page 0 */
- u8 gp_dma_ext_pg_3; /* GP-DMA channel extended page 0 */
- u8 gp_dma_ext_pg_5; /* GP-DMA channel extended page 0 */
- u8 gp_dma_ext_pg_6; /* GP-DMA channel extended page 0 */
- u8 gp_dma_ext_pg_7; /* GP-DMA channel extended page 0 */
- u8 pad_0xd8d[0x03];
- u8 gpdmaexttc3; /* GP-DMA channel 3 extender transfer count */
- u8 gpdmaexttc5; /* GP-DMA channel 5 extender transfer count */
- u8 gpdmaexttc6; /* GP-DMA channel 6 extender transfer count */
- u8 gpdmaexttc7; /* GP-DMA channel 7 extender transfer count */
- u8 pad_0xd94[0x4];
- u8 gpdmabcctl; /* buffer chaining control */
- u8 gpdmabcsta; /* buffer chaining status */
- u8 gpdmabsintenb; /* buffer chaining interrupt enable */
- u8 gpdmabcval; /* buffer chaining valid */
- u8 pad_0xd9c[0x04];
- u16 gpdmanxtaddl3; /* GP-DMA channel 3 next address low */
- u16 gpdmanxtaddh3; /* GP-DMA channel 3 next address high */
- u16 gpdmanxtaddl5; /* GP-DMA channel 5 next address low */
- u16 gpdmanxtaddh5; /* GP-DMA channel 5 next address high */
- u16 gpdmanxtaddl6; /* GP-DMA channel 6 next address low */
- u16 gpdmanxtaddh6; /* GP-DMA channel 6 next address high */
- u16 gpdmanxtaddl7; /* GP-DMA channel 7 next address low */
- u16 gpdmanxtaddh7; /* GP-DMA channel 7 next address high */
- u16 gpdmanxttcl3; /* GP-DMA channel 3 next transfer count low */
- u16 gpdmanxttch3; /* GP-DMA channel 3 next transfer count high */
- u16 gpdmanxttcl5; /* GP-DMA channel 5 next transfer count low */
- u16 gpdmanxttch5; /* GP-DMA channel 5 next transfer count high */
- u16 gpdmanxttcl6; /* GP-DMA channel 6 next transfer count low */
- u16 gpdmanxttch6; /* GP-DMA channel 6 next transfer count high */
- u16 gpdmanxttcl7; /* GP-DMA channel 7 next transfer count low */
- u16 gpdmanxttch7; /* GP-DMA channel 7 next transfer count high */
-
- u8 pad_0xdc0[0x0240];
-} sc520_mmcr_t;
-
-extern sc520_mmcr_t *sc520_mmcr;
-
-#endif
-
-/* Memory Mapped Control Registers (MMCR) Base Address */
-#define SC520_MMCR_BASE 0xfffef000
-
-/* MMCR Addresses (required for assembler code) */
-#define SC520_DRCCTL (SC520_MMCR_BASE + 0x010)
-#define SC520_DRCTMCTL (SC520_MMCR_BASE + 0x012)
-#define SC520_DRCCFG (SC520_MMCR_BASE + 0x014)
-#define SC520_DRCBENDADR (SC520_MMCR_BASE + 0x018)
-#define SC520_ECCCTL (SC520_MMCR_BASE + 0x020)
-#define SC520_DBCTL (SC520_MMCR_BASE + 0x040)
-#define SC520_ECCINT (SC520_MMCR_BASE + 0xd18)
-
-#define SC520_PAR0 (SC520_MMCR_BASE + 0x088)
-#define SC520_PAR1 (SC520_PAR0 + (0x04 * 1))
-#define SC520_PAR2 (SC520_PAR0 + (0x04 * 2))
-#define SC520_PAR3 (SC520_PAR0 + (0x04 * 3))
-#define SC520_PAR4 (SC520_PAR0 + (0x04 * 4))
-#define SC520_PAR5 (SC520_PAR0 + (0x04 * 5))
-#define SC520_PAR6 (SC520_PAR0 + (0x04 * 6))
-#define SC520_PAR7 (SC520_PAR0 + (0x04 * 7))
-#define SC520_PAR8 (SC520_PAR0 + (0x04 * 8))
-#define SC520_PAR9 (SC520_PAR0 + (0x04 * 9))
-#define SC520_PAR10 (SC520_PAR0 + (0x04 * 10))
-#define SC520_PAR11 (SC520_PAR0 + (0x04 * 11))
-#define SC520_PAR12 (SC520_PAR0 + (0x04 * 12))
-#define SC520_PAR13 (SC520_PAR0 + (0x04 * 13))
-#define SC520_PAR14 (SC520_PAR0 + (0x04 * 14))
-#define SC520_PAR15 (SC520_PAR0 + (0x04 * 15))
-
-/*
- * PARs for maximum allowable 256MB of SDRAM @ 0x00000000
- * Two PARs are required due to maximum PAR size of 128MB
- * These are used in the SDRAM sizing code to disable caching
- *
- * 111 0 0 0 1 11111111111 00000000000000 }- 0xe3ffc000
- * 111 0 0 0 1 11111111111 00100000000000 }- 0xe3ffc800
- * \ / | | | | \----+----/ \-----+------/
- * | | | | | | +---------- Start at 0x00000000
- * | | | | | | 0x08000000
- * | | | | | +----------------------- 128MB Region Size
- * | | | | | ((2047 + 1) * 64kB)
- * | | | | +------------------------------ 64kB Page Size
- * | | | +-------------------------------- Writes Enabled
- * | | +---------------------------------- Caching Enabled
- * | +------------------------------------ Execution Enabled
- * +--------------------------------------- SDRAM
- */
-#define SC520_SDRAM1_PAR 0xe3ffc000
-#define SC520_SDRAM2_PAR 0xe3ffc800
-
-#define SC520_PAR_WRITE_DIS 0x04000000
-#define SC520_PAR_CACHE_DIS 0x08000000
-#define SC520_PAR_EXEC_DIS 0x10000000
-
-/*
- * Programmable Address Regions to cover 256MB SDRAM (Maximum supported)
- * required for DRAM sizing code
- */
-
-/* MMCR Register bits (not all of them :) ) */
-
-/* SSI Stuff */
-#define CTL_CLK_SEL_4 0x00 /* Nominal Bit Rate = 8 MHz */
-#define CTL_CLK_SEL_8 0x10 /* Nominal Bit Rate = 4 MHz */
-#define CTL_CLK_SEL_16 0x20 /* Nominal Bit Rate = 2 MHz */
-#define CTL_CLK_SEL_32 0x30 /* Nominal Bit Rate = 1 MHz */
-#define CTL_CLK_SEL_64 0x40 /* Nominal Bit Rate = 512 KHz */
-#define CTL_CLK_SEL_128 0x50 /* Nominal Bit Rate = 256 KHz */
-#define CTL_CLK_SEL_256 0x60 /* Nominal Bit Rate = 128 KHz */
-#define CTL_CLK_SEL_512 0x70 /* Nominal Bit Rate = 64 KHz */
-
-#define TC_INT_ENB 0x08 /* Transaction Complete Interrupt Enable */
-#define PHS_INV_ENB 0x04 /* SSI Inverted Phase Mode Enable */
-#define CLK_INV_ENB 0x02 /* SSI Inverted Clock Mode Enable */
-#define MSBF_ENB 0x01 /* SSI Most Significant Bit First Mode Enable */
-
-#define SSICMD_CMD_SEL_XMITRCV 0x03 /* Simultaneous Transmit / Receive Transaction */
-#define SSICMD_CMD_SEL_RCV 0x02 /* Receive Transaction */
-#define SSICMD_CMD_SEL_XMIT 0x01 /* Transmit Transaction */
-#define SSISTA_BSY 0x02 /* SSI Busy */
-#define SSISTA_TC_INT 0x01 /* SSI Transaction Complete Interrupt */
-
-/* BITS for SC520_ADDDECCTL: */
-#define WPV_INT_ENB 0x80 /* Write-Protect Violation Interrupt Enable */
-#define IO_HOLE_DEST_PCI 0x10 /* I/O Hole Access Destination */
-#define RTC_DIS 0x04 /* RTC Disable */
-#define UART2_DIS 0x02 /* UART2 Disable */
-#define UART1_DIS 0x01 /* UART1 Disable */
-
-/*
- * Defines used for SDRAM Sizing (number of columns and rows)
- * Refer to section 10.6.4 - SDRAM Sizing Algorithm in the
- * Elan SC520 Microcontroller User's Manual (Order #22004B)
- */
-#define CACHELINESZ 0x00000010
-
-#define COL11_ADR 0x0e001e00
-#define COL10_ADR 0x0e000e00
-#define COL09_ADR 0x0e000600
-#define COL08_ADR 0x0e000200
-#define COL11_DATA 0x0b0b0b0b
-#define COL10_DATA 0x0a0a0a0a
-#define COL09_DATA 0x09090909
-#define COL08_DATA 0x08080808
-
-#define ROW14_ADR 0x0f000000
-#define ROW13_ADR 0x07000000
-#define ROW12_ADR 0x03000000
-#define ROW11_ADR 0x01000000
-#define ROW10_ADR 0x00000000
-#define ROW14_DATA 0x3f3f3f3f
-#define ROW13_DATA 0x1f1f1f1f
-#define ROW12_DATA 0x0f0f0f0f
-#define ROW11_DATA 0x07070707
-#define ROW10_DATA 0xaaaaaaaa
-
-/* 0x28000000 - 0x3fffffff is used by the flash banks */
-
-/* 0x40000000 - 0xffffffff is not adressable by the SC520 */
-
-/* priority numbers used for interrupt channel mappings */
-#define SC520_IRQ_DISABLED 0
-#define SC520_IRQ0 1
-#define SC520_IRQ1 2
-#define SC520_IRQ2 4 /* same as IRQ9 */
-#define SC520_IRQ3 11
-#define SC520_IRQ4 12
-#define SC520_IRQ5 13
-#define SC520_IRQ6 21
-#define SC520_IRQ7 22
-#define SC520_IRQ8 3
-#define SC520_IRQ9 4
-#define SC520_IRQ10 5
-#define SC520_IRQ11 6
-#define SC520_IRQ12 7
-#define SC520_IRQ13 8
-#define SC520_IRQ14 9
-#define SC520_IRQ15 10
-
-#endif
diff --git a/arch/x86/include/asm/ic/ssi.h b/arch/x86/include/asm/ic/ssi.h
deleted file mode 100644
index bd48eab..0000000
--- a/arch/x86/include/asm/ic/ssi.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * (C) Copyright 2008
- * Graeme Russ <graeme.russ@gmail.com>.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _ASM_IC_SSI_H_
-#define _ASM_IC_SSI_H_ 1
-
-int ssi_set_interface(int, int, int, int);
-void ssi_chip_select(int);
-u8 ssi_txrx_byte(u8);
-void ssi_tx_byte(u8);
-u8 ssi_rx_byte(void);
-
-
-#endif
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 6682e0d..d2dd6fd 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -35,7 +35,6 @@
#include <asm/realmode.h>
#include <asm/byteorder.h>
#include <asm/bootparam.h>
-#include <asm/ic/sc520.h>
/*
* Memory lay-out:
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index 2a5636c..c4ed820 100644
--- a/board/eNET/eNET.c
+++ b/board/eNET/eNET.c
@@ -23,7 +23,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/ic/sc520.h>
+#include <asm/arch/sc520.h>
#include <net.h>
#include <netdev.h>
diff --git a/board/eNET/eNET_pci.c b/board/eNET/eNET_pci.c
index d97387e..29d13d2 100644
--- a/board/eNET/eNET_pci.c
+++ b/board/eNET/eNET_pci.c
@@ -27,7 +27,7 @@
#include <common.h>
#include <pci.h>
#include <asm/pci.h>
-#include <asm/ic/pci.h>
+#include <asm/arch/pci.h>
static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S
index 77e5519..4241f6e 100644
--- a/board/eNET/eNET_start16.S
+++ b/board/eNET/eNET_start16.S
@@ -27,11 +27,9 @@
* that is used by U-boot to its final destination.
*/
-/* #include <asm/ic/sc520_defs.h> */
-
#include "config.h"
#include "hardware.h"
-#include <asm/ic/sc520.h>
+#include <asm/arch/sc520.h>
.text
.section .start16, "ax"
--
1.7.5.2.317.g391b14
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH 3/3] sc520: Create arch asm-offsets
2011-08-28 13:03 [U-Boot] [PATCH 0/3] Makefile & x86 - Move to generic include/asm/arch/asm-offsets.h Graeme Russ
2011-08-28 13:03 ` [U-Boot] [PATCH 1/3] Makefile: Add generic build rules for include/asm/arch/asm-offsets.h Graeme Russ
2011-08-28 13:03 ` [U-Boot] [PATCH 2/3] x86: Rename include/asm/ic to include/asm/arch-sc520 Graeme Russ
@ 2011-08-28 13:03 ` Graeme Russ
2011-08-30 17:51 ` [U-Boot] [PATCH 0/3] Makefile & x86 - Move to generic include/asm/arch/asm-offsets.h Mike Frysinger
3 siblings, 0 replies; 7+ messages in thread
From: Graeme Russ @ 2011-08-28 13:03 UTC (permalink / raw
To: u-boot
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
arch/x86/cpu/Makefile | 3 ++
arch/x86/cpu/sc520/Makefile | 2 +
arch/x86/cpu/sc520/asm-offsets.c | 45 +++++++++++++++++++++++++++++++
arch/x86/cpu/sc520/sc520_car.S | 3 +-
arch/x86/cpu/start.S | 3 +-
arch/x86/include/asm/arch-sc520/sc520.h | 26 ------------------
arch/x86/include/asm/global_data.h | 19 -------------
board/eNET/eNET_start16.S | 5 ++-
8 files changed, 57 insertions(+), 49 deletions(-)
create mode 100644 arch/x86/cpu/sc520/asm-offsets.c
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 7f1fc18..f88aa5f 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -40,6 +40,9 @@ all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+$(OBJS) \
+$(START): $(TOPDIR)/include/asm/arch/asm-offsets.h
+
#########################################################################
# defines $(obj).depend target
diff --git a/arch/x86/cpu/sc520/Makefile b/arch/x86/cpu/sc520/Makefile
index f462264..e1ef98d 100644
--- a/arch/x86/cpu/sc520/Makefile
+++ b/arch/x86/cpu/sc520/Makefile
@@ -48,6 +48,8 @@ all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+$(OBJS) : $(TOPDIR)/include/asm/arch/asm-offsets.h
+
#########################################################################
# defines $(obj).depend target
diff --git a/arch/x86/cpu/sc520/asm-offsets.c b/arch/x86/cpu/sc520/asm-offsets.c
new file mode 100644
index 0000000..794f00c
--- /dev/null
+++ b/arch/x86/cpu/sc520/asm-offsets.c
@@ -0,0 +1,45 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/arch/sc520.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+ DEFINE(GENERATED_GD_RELOC_OFF, offsetof(gd_t, reloc_off));
+
+ DEFINE(GENERATED_SC520_PAR0, offsetof(struct sc520_mmcr, par[0]));
+ DEFINE(GENERATED_SC520_PAR1, offsetof(struct sc520_mmcr, par[1]));
+ DEFINE(GENERATED_SC520_PAR2, offsetof(struct sc520_mmcr, par[2]));
+ DEFINE(GENERATED_SC520_PAR3, offsetof(struct sc520_mmcr, par[3]));
+ DEFINE(GENERATED_SC520_PAR4, offsetof(struct sc520_mmcr, par[4]));
+ DEFINE(GENERATED_SC520_PAR5, offsetof(struct sc520_mmcr, par[5]));
+ DEFINE(GENERATED_SC520_PAR6, offsetof(struct sc520_mmcr, par[6]));
+ DEFINE(GENERATED_SC520_PAR7, offsetof(struct sc520_mmcr, par[7]));
+ DEFINE(GENERATED_SC520_PAR8, offsetof(struct sc520_mmcr, par[8]));
+ DEFINE(GENERATED_SC520_PAR9, offsetof(struct sc520_mmcr, par[9]));
+ DEFINE(GENERATED_SC520_PAR10, offsetof(struct sc520_mmcr, par[10]));
+ DEFINE(GENERATED_SC520_PAR11, offsetof(struct sc520_mmcr, par[11]));
+ DEFINE(GENERATED_SC520_PAR12, offsetof(struct sc520_mmcr, par[12]));
+ DEFINE(GENERATED_SC520_PAR13, offsetof(struct sc520_mmcr, par[13]));
+ DEFINE(GENERATED_SC520_PAR14, offsetof(struct sc520_mmcr, par[14]));
+ DEFINE(GENERATED_SC520_PAR15, offsetof(struct sc520_mmcr, par[15]));
+
+ return 0;
+}
diff --git a/arch/x86/cpu/sc520/sc520_car.S b/arch/x86/cpu/sc520/sc520_car.S
index 7cac4d1..c66df58 100644
--- a/arch/x86/cpu/sc520/sc520_car.S
+++ b/arch/x86/cpu/sc520/sc520_car.S
@@ -24,6 +24,7 @@
#include <config.h>
#include <asm/processor-flags.h>
#include <asm/arch/sc520.h>
+#include <asm/arch/asm-offsets.h>
.section .text
@@ -55,7 +56,7 @@ car_init:
/* Configure Cache-As-RAM PAR */
movl $CONFIG_SYS_SC520_CAR_PAR, %eax
- movl $SC520_PAR2, %edi
+ movl $(SC520_MMCR_BASE + GENERATED_SC520_PAR2), %edi
movl %eax, (%edi)
/* Trash the cache then turn it on */
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 306fb49..4a34e37 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -30,6 +30,7 @@
#include <version.h>
#include <asm/global_data.h>
#include <asm/processor-flags.h>
+#include <asm/arch/asm-offsets.h>
.section .text
.code32
@@ -114,7 +115,7 @@ relocate_code:
/* Setup call address of in-RAM copy of board_init_r() */
movl $board_init_r, %ebp
- addl (GD_RELOC_OFF * 4)(%edx), %ebp
+ addl (GENERATED_GD_RELOC_OFF)(%edx), %ebp
/* Setup parameters to board_init_r() */
movl %edx, %eax
diff --git a/arch/x86/include/asm/arch-sc520/sc520.h b/arch/x86/include/asm/arch-sc520/sc520.h
index 5ac9bb8..9dc29d3 100644
--- a/arch/x86/include/asm/arch-sc520/sc520.h
+++ b/arch/x86/include/asm/arch-sc520/sc520.h
@@ -259,32 +259,6 @@ extern sc520_mmcr_t *sc520_mmcr;
/* Memory Mapped Control Registers (MMCR) Base Address */
#define SC520_MMCR_BASE 0xfffef000
-/* MMCR Addresses (required for assembler code) */
-#define SC520_DRCCTL (SC520_MMCR_BASE + 0x010)
-#define SC520_DRCTMCTL (SC520_MMCR_BASE + 0x012)
-#define SC520_DRCCFG (SC520_MMCR_BASE + 0x014)
-#define SC520_DRCBENDADR (SC520_MMCR_BASE + 0x018)
-#define SC520_ECCCTL (SC520_MMCR_BASE + 0x020)
-#define SC520_DBCTL (SC520_MMCR_BASE + 0x040)
-#define SC520_ECCINT (SC520_MMCR_BASE + 0xd18)
-
-#define SC520_PAR0 (SC520_MMCR_BASE + 0x088)
-#define SC520_PAR1 (SC520_PAR0 + (0x04 * 1))
-#define SC520_PAR2 (SC520_PAR0 + (0x04 * 2))
-#define SC520_PAR3 (SC520_PAR0 + (0x04 * 3))
-#define SC520_PAR4 (SC520_PAR0 + (0x04 * 4))
-#define SC520_PAR5 (SC520_PAR0 + (0x04 * 5))
-#define SC520_PAR6 (SC520_PAR0 + (0x04 * 6))
-#define SC520_PAR7 (SC520_PAR0 + (0x04 * 7))
-#define SC520_PAR8 (SC520_PAR0 + (0x04 * 8))
-#define SC520_PAR9 (SC520_PAR0 + (0x04 * 9))
-#define SC520_PAR10 (SC520_PAR0 + (0x04 * 10))
-#define SC520_PAR11 (SC520_PAR0 + (0x04 * 11))
-#define SC520_PAR12 (SC520_PAR0 + (0x04 * 12))
-#define SC520_PAR13 (SC520_PAR0 + (0x04 * 13))
-#define SC520_PAR14 (SC520_PAR0 + (0x04 * 14))
-#define SC520_PAR15 (SC520_PAR0 + (0x04 * 15))
-
/*
* PARs for maximum allowable 256MB of SDRAM @ 0x00000000
* Two PARs are required due to maximum PAR size of 128MB
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index f8a16d6..f977dbe 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -58,25 +58,6 @@ extern gd_t *gd;
#endif
-/* Word Offsets into Global Data - MUST match struct gd_t */
-#define GD_BD 0
-#define GD_FLAGS 1
-#define GD_BAUDRATE 2
-#define GD_HAVE_CONSOLE 3
-#define GD_RELOC_OFF 4
-#define GD_LOAD_OFF 5
-#define GD_ENV_ADDR 6
-#define GD_ENV_VALID 7
-#define GD_CPU_CLK 8
-#define GD_BUS_CLK 9
-#define GD_RELOC_ADDR 10
-#define GD_START_ADDR_SP 11
-#define GD_RAM_SIZE 12
-#define GD_RESET_STATUS 13
-#define GD_JT 14
-
-#define GD_SIZE 15
-
/*
* Global Data Flags
*/
diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S
index 4241f6e..f94b3b6 100644
--- a/board/eNET/eNET_start16.S
+++ b/board/eNET/eNET_start16.S
@@ -30,6 +30,7 @@
#include "config.h"
#include "hardware.h"
#include <asm/arch/sc520.h>
+#include <asm/arch/asm-offsets.h>
.text
.section .start16, "ax"
@@ -46,12 +47,12 @@ board_init16:
movw %ax, %ds
/* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
- movl $(SC520_PAR14 - SC520_MMCR_BASE), %edi
+ movl $GENERATED_SC520_PAR14, %edi
movl $CONFIG_SYS_SC520_BOOTCS_PAR, %eax
movl %eax, (%di)
/* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */
- movl $(SC520_PAR15 - SC520_MMCR_BASE), %edi
+ movl $GENERATED_SC520_PAR15, %edi
movl $CONFIG_SYS_SC520_LLIO_PAR, %eax
movl %eax, (%di)
--
1.7.5.2.317.g391b14
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH 0/3] Makefile & x86 - Move to generic include/asm/arch/asm-offsets.h
2011-08-28 13:03 [U-Boot] [PATCH 0/3] Makefile & x86 - Move to generic include/asm/arch/asm-offsets.h Graeme Russ
` (2 preceding siblings ...)
2011-08-28 13:03 ` [U-Boot] [PATCH 3/3] sc520: Create arch asm-offsets Graeme Russ
@ 2011-08-30 17:51 ` Mike Frysinger
3 siblings, 0 replies; 7+ messages in thread
From: Mike Frysinger @ 2011-08-30 17:51 UTC (permalink / raw
To: u-boot
On Sunday, August 28, 2011 09:03:10 Graeme Russ wrote:
> This series creates build rules to create (and clean)
> include/asm/arch/asm-offsets.h from an asm-offsets.c file located in the
> SoC directory. In particular, the new rules will skip creating the
> asm-offsets.h file if the SoC does not have an asm-offsets.c file
i think you're colliding with Stefano Babic's recent work:
[PATCH] Makefile : fix generation of cpu related asm-offsets.h
probably want to sync ;)
-mike
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^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH 1/3] Makefile: Add generic build rules for include/asm/arch/asm-offsets.h
2011-08-28 13:03 ` [U-Boot] [PATCH 1/3] Makefile: Add generic build rules for include/asm/arch/asm-offsets.h Graeme Russ
@ 2011-10-17 20:01 ` Wolfgang Denk
2011-10-21 21:25 ` Albert ARIBAUD
1 sibling, 0 replies; 7+ messages in thread
From: Wolfgang Denk @ 2011-10-17 20:01 UTC (permalink / raw
To: u-boot
Dear Albert,
In message <1314536593-14310-2-git-send-email-graeme.russ@gmail.com> Graeme Russ wrote:
>
> Add three features to the top-level makefile:
> - Add include/asm/arch/asm-offsets.h as a dependency of the 'depend'
> target to eliminate 'file does not exist' errors during dependency
> building
> - Skip generation of include/asm/arch/asm-offsets.h if the source file
> ($(CPUDIR)/$(SOC)/asm-offsets.c) does not exist
> - Add removal of arch specific asm-offsets.s and asm-offsets.h files to
> the 'clean' target
>
> Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
> ---
> Big Fat Note: I have not tested this on ARM which needs to be looked at
> closely as the SoC files are one level deeper than where sc520 sits under
> x86
>
> Makefile | 24 ++++++++++++++++++++++--
> 1 files changed, 22 insertions(+), 2 deletions(-)
Would you please ACK or NAK this patch?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Am besten betrachten Sie Fehlermeldungen als eine Art Psycho-Test,
mit dem herausgefunden werden soll, wie belastbar Sie sind."
- Dr. R. Wonneberger, Kompaktf?hrer LaTeX, Kap. 1.6: Fehlermeldungen
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH 1/3] Makefile: Add generic build rules for include/asm/arch/asm-offsets.h
2011-08-28 13:03 ` [U-Boot] [PATCH 1/3] Makefile: Add generic build rules for include/asm/arch/asm-offsets.h Graeme Russ
2011-10-17 20:01 ` Wolfgang Denk
@ 2011-10-21 21:25 ` Albert ARIBAUD
1 sibling, 0 replies; 7+ messages in thread
From: Albert ARIBAUD @ 2011-10-21 21:25 UTC (permalink / raw
To: u-boot
Hi Greame,
Le 28/08/2011 15:03, Graeme Russ a ?crit :
>
> Add three features to the top-level makefile:
> - Add include/asm/arch/asm-offsets.h as a dependency of the 'depend'
> target to eliminate 'file does not exist' errors during dependency
> building
> - Skip generation of include/asm/arch/asm-offsets.h if the source file
> ($(CPUDIR)/$(SOC)/asm-offsets.c) does not exist
> - Add removal of arch specific asm-offsets.s and asm-offsets.h files to
> the 'clean' target
>
> Signed-off-by: Graeme Russ<graeme.russ@gmail.com>
> ---
> Big Fat Note: I have not tested this on ARM which needs to be looked at
> closely as the SoC files are one level deeper than where sc520 sits under
> x86
>
> Makefile | 24 ++++++++++++++++++++++--
> 1 files changed, 22 insertions(+), 2 deletions(-)
This does not apply cleanly any more. Can you rebase?
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2011-10-21 21:25 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2011-08-28 13:03 [U-Boot] [PATCH 0/3] Makefile & x86 - Move to generic include/asm/arch/asm-offsets.h Graeme Russ
2011-08-28 13:03 ` [U-Boot] [PATCH 1/3] Makefile: Add generic build rules for include/asm/arch/asm-offsets.h Graeme Russ
2011-10-17 20:01 ` Wolfgang Denk
2011-10-21 21:25 ` Albert ARIBAUD
2011-08-28 13:03 ` [U-Boot] [PATCH 2/3] x86: Rename include/asm/ic to include/asm/arch-sc520 Graeme Russ
2011-08-28 13:03 ` [U-Boot] [PATCH 3/3] sc520: Create arch asm-offsets Graeme Russ
2011-08-30 17:51 ` [U-Boot] [PATCH 0/3] Makefile & x86 - Move to generic include/asm/arch/asm-offsets.h Mike Frysinger
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