From: Bjorn Helgaas <helgaas@kernel.org>
To: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Cc: tony.luck@intel.com, linux-pci@vger.kernel.org,
robert.moore@intel.com, linux-kernel@vger.kernel.org,
linux-acpi@vger.kernel.org, bp@alien8.de, bhelgaas@google.com,
james.morse@arm.com, acpica-devel@lists.linuxfoundation.org,
lenb@kernel.org
Subject: Re: [Acpica-devel] [PATCH v3 3/5] PCI: Add PCIe to PCI/PCI-X Bridge AER fields
Date: Thu, 10 Aug 2023 18:16:42 -0500 [thread overview]
Message-ID: <20230810231642.GA50403@bhelgaas> (raw)
In-Reply-To: <20230704120530.1322257-1-LeoLiu-oc@zhaoxin.com>
On Tue, Jul 04, 2023 at 08:05:30PM +0800, LeoLiu-oc wrote:
> From: leoliu-oc <leoliu-oc@zhaoxin.com>
>
> Define Secondary Uncorrectable Error Mask Register, Secondary
> Uncorrectable Error Severity Register and Secondary Error Capabilities and
> Control Register bits in AER capability for PCIe to PCI/PCI-X Bridge.
> Please refer to PCIe to PCI/PCI-X Bridge Specification, sec 5.2.3.2,
> 5.2.3.3 and 5.2.3.4.
>
> Signed-off-by: leoliu-oc <leoliu-oc@zhaoxin.com>
> ---
> include/uapi/linux/pci_regs.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index e5f558d964939..28e20c4d0afc3 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -800,6 +800,9 @@
> #define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */
> #define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */
> #define PCI_ERR_ROOT_ERR_SRC 0x34 /* Error Source Identification */
> +#define PCI_ERR_UNCOR_MASK2 0x30 /* PCIe to PCI/PCI-X Bridge */
> +#define PCI_ERR_UNCOR_SEVER2 0x34 /* PCIe to PCI/PCI-X Bridge */
> +#define PCI_ERR_CAP2 0x38 /* PCIe to PCI/PCI-X Bridge */
These need to line up with the offsets above, i.e.,
PCI_ERR_ROOT_ERR_SRC.
I think these should be named:
PCI_ERR_SEC_UNCOR_MASK
PCI_ERR_SEC_UNCOR_SEVER
PCI_ERR_SEC_ERR_CAP
because "Secondary" in this context doesn't have anything to do with
"2"; it just means the secondary (downstream) interface of the bridge.
Bjorn
prev parent reply other threads:[~2023-08-10 23:16 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-04 12:16 [Acpica-devel] [PATCH v3 3/5] PCI: Add PCIe to PCI/PCI-X Bridge AER fields LeoLiu-oc
2023-08-10 23:16 ` Bjorn Helgaas [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230810231642.GA50403@bhelgaas \
--to=helgaas@kernel.org \
--cc=LeoLiu-oc@zhaoxin.com \
--cc=acpica-devel@lists.linuxfoundation.org \
--cc=bhelgaas@google.com \
--cc=bp@alien8.de \
--cc=james.morse@arm.com \
--cc=lenb@kernel.org \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=robert.moore@intel.com \
--cc=tony.luck@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).